Search results for "0.8 micron"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya	An Efficient Parallel Prefix Sums Architecture with Domino Logic.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	shift switching, binary prefix sums, binary counting, VLSI design, scalable architectures, domino logic, Hardware-algorithms
1	Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya	An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. (PDF / PS)	IPPS/SPDP	1999	DBLP DOI BibTeX RDF	Special-purpose parallel architectures, digital signal processing, computer arithmetic, VLSI design, domino logic
1	Ramón González Carvajal, Antonio Torralba, Rafael L. Millán, Leopoldo García Franquelo	Automatic synthesis of analog and mixed-signal fuzzy controllers with emphasis in power consumption.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Giovanni Palmisano, Salvatore Pennisi	A 20-dB CMOS IF amplifier with embedded single-to-differential input converter.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Martin Benes, Steven M. Nowick, Andrew Wolfe	A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors.	ASYNC	1998	DBLP DOI BibTeX RDF	Huffman encoding, embedded systems, asynchronous, embedded processors, dynamic logic, hazards, digital design
1	Neil Harrison	Orphan Metal Removal as an Element of DFM. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	Layout modification, Yield, Design for manufacturability
1	Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta	Process Variations and their Impact on Circuit Operation. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	process parameters, electrical parameters, design corners, delay, correlations, process variations, crosstalk
1	Andrew A. Chien	A Cost and Speed Model for k-ary n-Cube Wormhole Routers.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	Routing networks, parallel computing, wormhole routing, adaptive routing, multicomputers, gate array, deadlock prevention
1	Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An	A Scalable Memory System Design.	VLSI Design	1997	DBLP DOI BibTeX RDF	scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed
1	Martin Benes, Andrew Wolfe, Steven M. Nowick	A High-Speed Asynchronous Decompression Circuit for Embedded Processors.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Navin Chaddha, Mohan Vishwanath	A low power video encoder with power, memory and bandwidth scalability.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power video encoder, power scalability, memory scalability, bandwidth scalability, portable video, generic block transform, memory rate distortion, perceptually weighted hierarchical vector quantization, 150 to 300 W, 0.8 micron, 1.5 V, video coding, power consumption, transform coding, table lookup, table lookup, CMOS technology, vector quantisation, block codes
1	Francis H. Y. Chan, Francis K. Lam, H. F. Li, J. G. Liu	An all adder systolic structure for fast computation of moments.	VLSI Signal Processing	1996	DBLP DOI BibTeX RDF
1	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
1	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation