Search results for "32 bit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Murat Aydos, T. Yanik, Çetin Kaya Koç	An High-Speed ECC-based Wireless Authentication Protocol on an ARM Microprocessor.	ACSAC	2000	DBLP DOI BibTeX RDF	high-speed ECC-based wireless authentication, ARM microprocessor, elliptic curve digital signature algorithm, ARM7TDMI processor, core processor, 80 MHz, 160 bit, mobile computing, elliptic curve cryptography, public key cryptography, software libraries, software library, authorisation, microprocessor chips, message authentication, portable computers, ECDSA, 32 bit, wireless applications
1	Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra	Fast and area-time efficient Berger code checkers. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	Berger code checker, ratioed FET circuit, area-time efficiency, resistive breaks, VLSI, defects, error detection codes, bridges, speed, threshold function, 32 bit, 1.2 micron
1	Shriram Kulkarni, Pinaki Mazumder, George I. Haddad	A high-speed 32-bit parallel correlator for spread spectrum communication.	VLSI Design	1996	DBLP DOI BibTeX RDF	pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence
1	I. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan	Circuit/architecture for low-power high-performance 32-bit adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
1	David M. Lewis	Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	read-only storage, interleaved memory function interpolators, accurate LNS arithmetic unit, accuracy requirements, round to nearest, 91 kbit, interpolation, digital arithmetic, polynomials, error analysis, floating point, approximation theory, ROM, polynomial interpolation, 32 bit, storage requirements
1	Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Mark D. Winkel	Applying Features of IEEE 754 to Sign/Logarithm Arithmetic.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	sign/logarithm arithmetic, standard floating point arithmetic, multilayer sign/logarithm format, denormalized values, NaNs, logarithmic denormalized arithmetic algorithms, standards, digital arithmetic, number theory, zeros, 32 bit, infinities, IEEE 754
1	Nhon T. Quach, Michael J. Flynn	High-Speed Addition in CMOS.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit
1	Veljko M. Milutinovic, David A. Fura, Walter A. Helbig	Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide
1	Walter A. Helbig, Veljko M. Milutinovic	A DCFL E/D-MESFET GaAs Experimental RISC Machine.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	RCA, DCFL E/D-MESFET, RISC machine, GaAs microprocessor, instruction execution sequence, III-V semiconductors, microprocessor chips, instruction set architecture, software environment, reduced instruction set computing, 32 bit, field effect integrated circuits, gallium arsenide