Search results for "3D integration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Wilfried Haensch	Why should we do 3D integration?	DAC	2008	DBLP DOI BibTeX RDF	many core systems, memory sub system, 3D integration
2	Yangyang Pan, Tong Zhang	DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dram-based fpga, memory stacking, 3d integration
2	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
2	Norman P. Jouppi, Yuan Xie	Emerging technologies and their impact on system design.	ISLPED	2009	DBLP DOI BibTeX RDF	new non-volatile memory technology, emerging technology, 3d integration
2	Robert Fischbach, Jens Lienig, Tilo Meister	From 3D circuit technologies and data structures to interconnect prediction.	SLIP	2009	DBLP DOI BibTeX RDF	3d floorplanning, three-dimensional circuits, data structures, 3d integration, interconnect prediction
2	Syed M. Alam, Mike Ignatowski, Yuan Xie	Technology, CAD tools, and designs for emerging 3D integration technology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D CAD, 3D IC
2	Wangyuan Zhang, Tao Li	Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.	MICRO	2008	DBLP DOI BibTeX RDF
2	Gabriel H. Loh	A modular 3d processor for flexible product design and technology migration.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	modular, superscalar, 3d-integration
2	Ahmed Maine Jerraya	System design for 3D Silicon integration.	SBCCI	2008	DBLP DOI BibTeX RDF	CAD, 3D-integration
2	Cesare Ferri, Sherief Reda, R. Iris Bahar	Parametric yield management for 3D ICs: Models and strategies for improvement.	JETC	2008	DBLP DOI BibTeX RDF	performance, process variations, leakage, 3D integration, yield management
2	Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong	Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.	JETC	2008	DBLP DOI BibTeX RDF	3D packing, microarchitecture, 3D integration, thermal
2	Syed M. Alam, Robert E. Jones, Shahid Rauf, Ritwik Chatterjee	Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology.	ISQED	2007	DBLP DOI BibTeX RDF
2	Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong	Fine grain 3D integration for microarchitecture design through cube packing exploration.	ICCD	2007	DBLP DOI BibTeX RDF
2	Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein	Design space exploration for 3D architectures.	JETC	2006	DBLP DOI BibTeX RDF	hardware, microarchitecture, processor architectures, 3D integration
2	Sachin S. Sapatnekar, Kevin J. Nowka	Guest Editors' Introduction: New Dimensions in 3D Integration.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	wafer stacking, silicon processing, FPGA, architecture, CAD tools, 3D integration, 3D design
2	Rajesh K. Gupta	Going 3D: Silicon and D&T.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	vertical stacking, wireless, EDA, cell phone, 3D integration, International Test Conference
1	Cheng-Ta Ko, Kuan-Neng Chen	Low temperature bonding technology for 3D integration.	Microelectronics Reliability	2012	DBLP DOI BibTeX RDF
1	S. L. Lin, W. C. Huang, C. T. Ko, Kuan-Neng Chen	BCB-to-oxide bonding technology for 3D integration.	Microelectronics Reliability	2012	DBLP DOI BibTeX RDF
1	Chang Liu, Sung Kyu Lim	A design tradeoff study with monolithic 3D integration.	ISQED	2012	DBLP DOI BibTeX RDF
1	Hongbin Sun, Pengju Ren, Nanning Zheng, Tong Zhang, Tao Li	Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Zine Abid, Ming Liu, Wei Wang 0003	3D Integration of CMOL Structures for FPGA Applications.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Mukta G. Farooq, Subramanian S. Iyer	3D integration review.	SCIENCE CHINA Information Sciences	2011	DBLP DOI BibTeX RDF
1	W. R. Bottoms	Test challenges for 3D integration (an invited paper for CICC 2011).	CICC	2011	DBLP DOI BibTeX RDF
1	Rasit Onur Topaloglu	Applications driving 3D integration and corresponding manufacturing challenges.	DAC	2011	DBLP DOI BibTeX RDF
1	Shekhar Borkar	3D integration for energy efficient system design.	DAC	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou	Domain-specific processor with 3D integration for medical image processing.	ASAP	2011	DBLP DOI BibTeX RDF
1	Clinton K. Landrock, Badr Omrane, Yindar Chuo, Bozena Kaminska, Jeydmer Aristizabal	2D and 3D integration with organic and silicon electronics.	DATE	2011	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
1	Thorlindur Thorolfsson, Samson Melamed, W. Rhett Davis, Paul D. Franzon	Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Cheng-Ta Ko, Kuan-Neng Chen	Wafer-level bonding/stacking technology for 3D integration.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Marc Belleville	3D Integration for Digital and Imagers Circuits: Opportunities and Challenges.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
1	Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai	Silicon 3D-integration technology and systems.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Jin-Fu Li, Cheng-Wen Wu	Is 3D integration an opportunity or just a hype?	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yuan Xie	Processor Architecture Design Using 3D Integration Technology.	VLSI Design	2010	DBLP DOI BibTeX RDF	3D Technology, Architeture
1	Armin Klumpp, Peter Ramm, Robert Wieland	3D-integration of silicon devices: A key technology for sophisticated products.	DATE	2010	DBLP BibTeX RDF
1	Christophe Zinck	3D integration infrastructure & market status.	3DIC	2010	DBLP DOI BibTeX RDF
1	Negin Golshani, Jaber Derakhshandeh, Ryoichi Ishihara, C. I. M. Beenakker, Michael Robertson, Thomas Morrison	Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon.	3DIC	2010	DBLP DOI BibTeX RDF
1	Christophe Zinck	Keynote speakers day 1: 3D integration with TSV interconnects: Technology trends & market analysis.	3DIC	2010	DBLP DOI BibTeX RDF
1	Cheng-Ta Ko, Kuan-Neng Chen, Wei-Chung Lo, Chuan-An Cheng, Wen-Chun Huang, Zhi-Cheng Hsiao, Huan-Chun Fu, Yu-Hua Chen	Wafer-level 3D integration using hybrid bonding.	3DIC	2010	DBLP DOI BibTeX RDF
1	Gweltaz Gaudin, Gregory Riou, Didier Landru, Catherine Tempesta, Ionut Radu, Mariam Sadaka, Kevin Winstel, Emily Kinser, Robert Hannon	Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment.	3DIC	2010	DBLP DOI BibTeX RDF
1	Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne	Cost effectiveness of 3D integration options.	3DIC	2010	DBLP DOI BibTeX RDF
1	Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma, Sayuri Kohara, Keiji Matsumoto, Hidekazu Kikuchi, Yasumitsu Orii, Toshiro Mitsuhashi, Fumiaki Yamada	High density 3D integration by pre-applied Inter Chip Fill.	3DIC	2010	DBLP DOI BibTeX RDF
1	Markus Gabriel, Thomas Knauer, Peter Bisson, Sumant Sood, Wilfried Bair, Jim Hermanowski	Equipment challenges and solutions for diverse temporary bonding and de-bonding processes in 3D integration.	3DIC	2010	DBLP DOI BibTeX RDF
1	Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon	Logic-on-logic 3D integration and placement.	3DIC	2010	DBLP DOI BibTeX RDF
1	Jeff Burns	3D integration - A server perspective.	3DIC	2010	DBLP DOI BibTeX RDF
1	Gregory Riou, Gweltaz Gaudin, Didier Landru, Catherine Tempesta, Ionut Radu, Mariam Sadaka, Kevin Winstel, Emily Kinser, Robert Hannon, Boris V. Kamenev, Michael Darwin, Robert Sachs	Pre bonding metrology solutions for 3D integration.	3DIC	2010	DBLP DOI BibTeX RDF
1	Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal	3D integration: Circuit design, test, and reliability challenges.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Tien-Hung Lin, Po-Tsang Huang, Wei Hwang	Power noise suppression technique using active decoupling capacitor for TSV 3D integration.	SoCC	2010	DBLP DOI BibTeX RDF
1	Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel Loh, Alok N. Choudhary	Quantifying and coping with parametric variations in 3D-stacked microarchitectures.	DAC	2010	DBLP DOI BibTeX RDF	processor pipeline, process variations, 3D integration, cache architectures
1	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
1	Jishen Zhao, Xiangyu Dong, Yuan Xie	Cost-aware three-dimensional (3D) many-core multiprocessor design.	DAC	2010	DBLP DOI BibTeX RDF	3D IC design, many-core processor design, cost modeling
1	Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer	Design of embedded MRAM macros for memory-in-logic applications.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	thermally assisted switching (tas), architecture, low power, system on chip (soc), embedded, mram, non-volatile
1	Yibo Chen, Jishen Zhao, Yuan Xie	3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.	ISLPED	2010	DBLP DOI BibTeX RDF	non-volatile FPGA, phase-change memory, 3D IC
1	Zongwu Tang	Efficient design practices for thermal management of a TSV based 3D IC system.	ISPD	2010	DBLP DOI BibTeX RDF	thermal gradient, placement, design rule, TSV
1	David S. Kung, Yuan Xie	Guest Editors' Introduction: Opportunities and Challenges of 3D Integration.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Peggy Aycinena	DATE 2009 Workshop on 3D Integration.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Syed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain	Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Using 3D integration technology to realize multi-context FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda	An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.	ISSCC	2009	DBLP DOI BibTeX RDF
1	F. Crnogorac, R. Birringer, R. Dauskardt, F. Pease	Aluminum-Germanium eutectic bonding for 3D integration.	3DIC	2009	DBLP DOI BibTeX RDF
1	Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisaski Kino, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi	Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.	3DIC	2009	DBLP DOI BibTeX RDF
1	Léa Di Cioccio, Pierric Gueguen, Rachid Taibi, Thomas Signamarcheix, Laurent Bally, Laurent Vandroux, Marc Zussy, Sophie Verrun, Jérôme Dechamp, Patrick Leduc, Myriam Assous, David Bouchu, François de Crecy, Laurent-Luc Chapelon, Laurent Clavelier	An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling.	3DIC	2009	DBLP DOI BibTeX RDF
1	Yoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi	3D integration technology for 3D stacked retinal chip.	3DIC	2009	DBLP DOI BibTeX RDF
1	Morihiro Kada	Development of Functionally innovative 3D-Integrated Circuit (Dream Chip) technology / High-Density 3D-Integration Technology for Multifunctional Devices.	3DIC	2009	DBLP DOI BibTeX RDF
1	David Henry, Séverine Cheramy, Jean Charbonnier, Pascal Chausse, Muriel Neyret, Cathy Brunet-Manquat, Sophie Verrun, Nicolas Sillon, Laurent Bonnot, Xavier Gagnard, E. Saugier	3D integration technology for set-top box application.	3DIC	2009	DBLP DOI BibTeX RDF
1	Julie Roullard, Stéphane Capraro, Thierry Lacrevaz, Lionel Cadix, Elie Eid, Alexis Farcy, Bernard Fléchet	Influence of 3D integration on 2D interconnections and 2D self inductors HF properties.	3DIC	2009	DBLP DOI BibTeX RDF
1	Thorlindur Thorolfsson, Samson Melamed, Gary Charles, Paul D. Franzon	Comparative analysis of two 3D integration implementations of a SAR processor.	3DIC	2009	DBLP DOI BibTeX RDF
1	Chang-Lee Chen, D.-R. Yost, Jeffrey M. Knecht, David C. Chapman, Douglas C. Oakley, Leonard J. Mahoney, Joseph P. Donnelly, Antonio M. Soares, Vyshnavi Suntharalingam, Robert Berger, V. Bolkhovsky, W. Hu, Bruce D. Wheeler, Craig L. Keast, David C. Shaver	Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits.	3DIC	2009	DBLP DOI BibTeX RDF
1	Wojciech Maly	Vertical slit transistor based integrated circuits (VeSTICs) paradigm.	ISPD	2009	DBLP DOI BibTeX RDF	dual gate transistor, ic deign-manufacturing paradigm, vertical channel, vesfet, 3d integration, regular fabric, dfm
1	Charles Chiang, Subarna Sinha	The road to 3D EDA tool readiness.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Yuan Xie	System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Qi Wu, Jian-Qiang Lu, Kenneth Rose, Tong Zhang	Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	three-dimentional integration, dram, decoupling capacitor
1	Sherief Reda, Aung Si, R. Iris Bahar	Reducing the leakage and timing variability of 2D ICcs using 3D ICs.	ISLPED	2009	DBLP DOI BibTeX RDF	3D integrated circuit, timing, variability, leakage
1	Guangyu Sun, Xiaoxia Wu, Yuan Xie	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, performance, 3D, L2 caches
1	Thorlindur Thorolfsson, Nariman Moezzi Madani, Paul D. Franzon	A low power 3D integrated FFT engine using hypercube memory division.	ISLPED	2009	DBLP DOI BibTeX RDF	FFT, scaling, 3DIC
1	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
1	Bill R. Bottoms	Interconnect solutions for TeraScale computing.	SLIP	2009	DBLP DOI BibTeX RDF	interconnect
1	Yangyang Pan, Tong Zhang	Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.	ASAP	2009	DBLP DOI BibTeX RDF
1	Rakesh S. Anigundi, Hongbin Sun, Jian-Qiang Lu, Kenneth Rose, Tong Zhang	Architecture design exploration of three-dimensional (3D) integrated DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
1	José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici	Through Silicon Via-Based Grid for Thermal Control in 3D Chips.	NanoNet	2009	DBLP DOI BibTeX RDF
1	Peter Schneider, Sven Reitz, Andreas Wilde, Günter Elst, Peter Schwarz	Towards a Methodology for Analysis of Interconnect Structures for 3D-Integration of Micro Systems	CoRR	2008	DBLP BibTeX RDF
1	Rozalia Beica, Charles Sharbono, Tom Ritzdorf	Copper Electrodeposition for 3D Integration	CoRR	2008	DBLP BibTeX RDF
1	Steven J. Koester, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan-Neng Chen, Douglas C. La Tulipe Jr., Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis	Wafer-level 3D integration technology.	IBM Journal of Research and Development	2008	DBLP DOI BibTeX RDF
1	Robert E. Jones	Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology.	ISQED	2008	DBLP DOI BibTeX RDF
1	Bruno Bougard, Paul Marchal, Luca Benini, Doris Keitel-Schulz, N. Checka	HOT TOPIC - 3D Integration or How to Scale in the 21st Century.	DATE	2008	DBLP DOI BibTeX RDF
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda	Multilayer stacking technology using wafer-to-wafer stacked method.	JETC	2008	DBLP DOI BibTeX RDF	stacking process, design, hardware, 3D integration
1	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.	DAC	2008	DBLP DOI BibTeX RDF	3D stacking, MRAM
1	Xiuyi Zhou, Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0002	Thermal Management for 3D Processors via Task Scheduling.	ICPP	2008	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, André Ivanov	Novel interconnect infrastructures for massive multicore chips - an overview.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Kevin Ryan, Sansiri Tanachutiwat, Wei Wang 0003	3D CMOL Crossnet for Neuromorphic Network Applications.	NanoNet	2008	DBLP DOI BibTeX RDF	CMOS-Nano Hybrid System, CMOL, Crossnet, Neuromorphic Network, 3D IC
1	Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood	3D Integration for Introspection.	IEEE Micro	2007	DBLP DOI BibTeX RDF	3D interconnect, 3D stacking, performance evaluation, testing, debugging, profiling
1	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	A novel dimensionally-decomposed router for on-chip communication in 3D architectures.	ISCA	2007	DBLP DOI BibTeX RDF	3D architecture, 3D integration, network-on-chip (NoC)
1	Gabriel H. Loh, Yuan Xie, Bryan Black	Processor Design in 3D Die-Stacking Technologies.	IEEE Micro	2007	DBLP DOI BibTeX RDF	processor architectures, computer systems organization, 3D integration
1	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud	Thermally robust clocking schemes for 3D integrated circuits.	DATE	2007	DBLP DOI BibTeX RDF
1	Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang 0003	Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Cesare Ferri, Sherief Reda, R. Iris Bahar	Strategies for improving the parametric yield and profits of 3D ICs.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Zhaonian Zhang, Andreas G. Andreou	Design of An Ultra Wideband Transmitter in 0.18µm 3D Silicon on Insulator CMOS.	CISS	2007	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF