| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang 0002 (eds.) |
Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura |
Stepwise sleep depth control for run-time leakage power saving. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Saman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori |
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Zhao, Russell Tessier, Wayne Burleson |
Distributed sensor data processing for many-cores. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Youenn Corre, Jean-Philippe Diguet, Dominique Heller, Loïc Lagadec |
A framework for high-level synthesis of heterogeneous MP-SoC. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy |
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Grissom, Philip Brisk |
A high-performance online assay interpreter for digital microfluidic biochips. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahmoud Zangeneh, Ajay Joshi |
Performance and energy models for memristor-based 1T1R RRAM cell. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Laurent Bousquet, Emmanuel Simeu |
High-level modeling of power consumption in active linear analog circuits. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | In-Seok Jung, Yong-Bin Kim |
A low stand-by power start-up circuit for SMPS PWM controller. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamran Rahmani, Prabhat Mishra, Swarup Bhunia |
Memory-based computing for performance and energy improvement in multicore architectures. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pilin Junsangsri, Fabrizio Lombardi |
A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuo Wang, Mohammad Tehranipoor |
TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Masoud Zamani, Mehdi Baradaran Tahoori |
Reliable logic mapping on Nano-PLA architectures. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marzieh Morshedzadeh Morshedzadeh, Ali Jahanian |
Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Varadaraj Kamath Nileshwar, Roman Lysecky |
SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Libo Huang, Zhiying Wang, Nong Xiao |
An optimized multicore cache coherence design for exploiting communication locality. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Jongman Kim |
A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert |
WRIP: logic restructuring techniques for wirelength-driven incremental placement. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Keisuke Inoue, Mineo Kaneko |
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen |
Top-down-based symmetrical buffered clock routing. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza |
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
STEP: a unified design methodology for secure test and IP core protection. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok Kumar Palaniswamy, Spyros Tragoudas |
A scalable threshold logic synthesis method using ZBDDs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young |
Crosslink insertion for variation-driven clock network construction. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Mazumdar, Mircea Stan |
Breaking the power delivery wall using voltage stacking. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Renatas Jakushokas, Eby G. Friedman |
Link breaking methodology: mitigating noise within power networks. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
NBTI effects on tree-like clock distribution networks. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Luís Guerra e Silva |
Unifying functional and parametric timing verification. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Curtis Andrus, Matthew R. Guthaus |
Lithography-aware layout compaction. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kotb Jabeur, Ian O'Connor, Nataliya Yakymets, Sébastien Le Beux |
Ambipolar double-gate FETs for the design of compact logic structures. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura |
A novel power-gating scheme utilizing data retentiveness on caches. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ying Teng, Baris Taskin |
Synchronization scheme for brick-based rotary oscillator arrays. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng |
Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled N. Salama |
Memristor: the illusive device. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter M. Maurer |
Extending symmetric variable-pair transitivities using state-space transformations. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Agathoklis Papadopoulos, Vasilis J. Promponas, Theocharis Theocharides |
Towards systolic hardware acceleration for local complexity analysis of massive genomic data. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhe Zhang, Michael A. Turi, José G. Delgado-Frias |
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Acquaviva, Nicola Bombieri, Franco Fummi, Sara Vinco |
On the automatic synthesis of parallel SW from RTL models of hardware IPs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Satoshi Goto |
Voltage island-driven power optimization for application specific network-on-chip design. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu |
An efficient approach for designing and minimizing reversible programmable logic arrays. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bojan Maric, Jaume Abella, Mateo Valero |
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Yang, Yong-bin Kim |
Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Manohar Ayinala, Keshab K. Parhi |
Parallel pipelined FFT architectures with reduced number of delays. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria |
A novel hybrid FIFO asynchronous clock domain crossing interfacing method. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Xie, Vijaykrishnan Narayanan, Yuan Xie |
Mitigating electromigration of power supply networks using bidirectional current stress. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujay Deb, Kevin Chang, Miralem Cosic, Amlan Ganguly, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer |
CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Huan Chen 0001, João Marques-Silva |
New & improved models for SAT-based bi-decomposition. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Al Davis |
The role of photonics in future data centers. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicholas Tuzzio, Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor |
A zero-overhead IC identification technique using clock sweeping and path delay analysis. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amlan Ganguly, Mohsin Yusuf Ahmed, Anuroop Vidapalapati |
A denial-of-service resilient wireless NoC architecture. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | David Brenner, Cory E. Merkel, Dhireesha Kudithipudi |
Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Eric Senn, Smaïl Niar |
An efficient power estimation methodology for complex RISC processor-based platforms. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen |
Density-reduction-oriented layer assignment for rectangle escape routing. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jacob Murray, John Klingner, Partha Pratim Pande, Behrooz Shirazi |
Sustainable multi-core architecture with on-chip wireless links. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava |
Design of an RNS reverse converter for a new five-moduli special set. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri |
Alleviating NBTI-induced failure in off-chip output drivers. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava, Prabhat Mishra |
Synergistic integration of code encryption and compression in embedded systems. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin 0001 |
A design approach dedicated to network-based and conflict-free parallel interleavers. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | HeungJun Jeon, Yong-Bin Kim |
A fully integrated switched-capacitor DC-DC converter with dual output for low power application. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayed Ahmad Salehi, Rasoul Amirfattahi, Keshab K. Parhi |
Efficient folded VLSI architectures for linear prediction error filters. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabrizio Lombardi, Wei Wei, Jie Han |
Modeling a single electron turnstile in HSPICE. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiajia Jiao, Yuzhuo Fu |
RAPA: reliability-aware priority arbitration strategy for network on chip. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pengpeng Chen, Bo Zhao, Rong Luo, Huazhong Yang |
A low-power all-digital GFSK demodulator with robust clock data recovery. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sadiq M. Sait, Abdalrahman M. Arafeh |
Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jifeng Chen, Shuo Wang, Mohammad Tehranipoor |
Efficient selection and analysis of critical-reliability paths and gates. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov |
Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov |
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dominik Gruber, Timm Ostermann |
Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Simone Corbetta, William Fornaciari |
NBTI mitigation in microprocessor designs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Osman Allam, Stijn Eyerman, Lieven Eeckhout |
An efficient CPI stack counter architecture for superscalar processors. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Arne Heittmann, Tobias G. Noll |
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph S. Friedman, Nikhil Rangaraju, Yehea I. Ismail, Bruce W. Wessels |
InMnAs magnetoresistive spin-diode logic. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xi Li, Gangyong Jia, Yun Chen, Zongwei Zhu, Xuehai Zhou |
Share memory aware scheduler: balancing performance and fairness. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori |
A linear programming approach for minimum NBTI vector selection. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinyu Li, Omar Hammami |
Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
Repeater insertion in power-managed VLSI systems. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fu Luo, Godi Fischer |
Low jitter audio range PLL with ultra low power dissipation. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Alipour, Mohammad Haji Seyed Javadi, Ali Jahanian |
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras |
Power estimation of dividers implemented in FPGAs. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta |
Enabling architectural innovations using non-volatile memory. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Supriyo Maji, Pradip Mandal |
A geometric programming aided knowledge based approach for analog circuit synthesis and sizing. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan |
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil |
Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ingrid Verbauwhede, Roel Maes |
Physically unclonable functions: manufacturing variability as an unclonable device identifier. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa |
An approximation algorithm for cofactoring-based synthesis. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro |
Design of low-power multiple constant multiplications using low-complexity minimum depth operations. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Adam C. Cabe, Mircea R. Stan |
Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hugues de Riedmatten |
Solid state optical quantum memories. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert |
Design of MRAM based logic circuits and its applications. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Farinaz Koushanfar |
Integrated circuits metering for piracy protection and digital rights management: an overview. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | André Lange, Joachim Haase, Hendrik T. Mau |
Fitting standard cell performance to generalized Lambda distributions. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino |
Buffering of frequent accesses for reduced cache aging. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Bouwens, Jos Huisken, Harmke de Groot, Martijn Bennebroek, Anteneh A. Abbo, Octavio Santana, Jef L. van Meerbergen, Antoine Fraboulet |
A dual-core system solution for wearable health monitors. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Hanyu |
Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bojan Mihajlovic, Zeljko Zilic |
Real-time address trace compression for emulated and real system-on-chip processor core debugging. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero |
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Singh, Jae-Cheol Son, Ukrae Cho, Gunok Jung, Min-Su Kim, Hyoungwook Lee, Suhwan Kim |
A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arne Heittmann, Tobias G. Noll |
Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg |
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
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