Search results for "ASIP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rudolf Mathar	Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.	CHES	2009	DBLP DOI BibTeX RDF	Barreto-Naehrig curves, elliptic-curve cryptography (ECC), design-space exploration, Application-specific instruction-set processor (ASIP), arithmetic, pairing-based cryptography
3	Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll	ASIP-eFPGA Architecture for Multioperable GNSS Receivers.	SAMOS	2008	DBLP DOI BibTeX RDF	arithmetic oriented eFPGA, multioperable GNSS, ASIP
3	Quang Dinh, Deming Chen, Martin D. F. Wong	Efficient ASIP design for configurable processors with fine-grained resource sharing.	FPGA	2008	DBLP DOI BibTeX RDF	multi-cycle IO, compilation, ASIP, resource sharing, configurable processor
3	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP architecture exploration for efficient IPSec encryption: A case study.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	computer-aided design, ADL, ASIP, IPSec
3	Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi	Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	ODYSSEY, embedded systems, ASIP, JPEG
3	Min Jiang, Bing Yang, Xinan Wang, Tianyi Zhang	SW/HW Co-design of a Java-based ASIP for Pervasive Computing in Mobile Applications.	DELTA	2004	DBLP DOI BibTeX RDF	SWHW Co-design, Java-based ASIP(JASIP), Pervasive Computing, Mobile Multimedia
3	Hideaki Yanagisawa, Minoru Uehara, Hideki Mori	Development Methodology of ASIP Based on Java Byte Code Using HW/SW Co-Design System for Processor Design.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	HW/SW Codesign system, C-DASH, ASIP, Java processor, ISA
3	Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr	A novel approach for flexible and consistent ADL-driven ASIP design.	DAC	2004	DBLP DOI BibTeX RDF	ADL, embedded processors, ASIP
3	Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran	Dual-pipeline heterogeneous ASIP design.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	dual-pipeline, instruction set generation, ASIP, superscalar
3	Tilman Glökler, Andreas Hoffmann, Heinrich Meyr	Methodical Low-Power ASIP Design Space Exploration.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
3	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
3	Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar	Exploring the Number of Register Windows in ASIP Synthesis.	VLSI Design	2002	DBLP DOI BibTeX RDF	Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows
2	Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar	Instruction Selection in ASIP Synthesis Using Functional Matching.	VLSI Design	2010	DBLP DOI BibTeX RDF	Functional Matching, ASIP, Covering, Confluence, Structural Matching
2	Hai Lin 0004, Yunsi Fei	A novel multi-objective instruction synthesis flow for application-specific instruction set processors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	instruction set synthesis, application-specific instruction set processor (ASIP)
2	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
2	Timo Vogt, Norbert Wehn	A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Sung Dae Kim, Myung Hoon Sunwoo	ASIP Approach for Implementation of H.264/AVC.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign
2	Li Zhang, Shuangfei Li, Zan Yin, Wenyuan Zhao	A Research on an ASIP Processing Element Architecture Suitable for FPGA Implementation.	CSSE	2008	DBLP DOI BibTeX RDF
2	Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen	Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.	HiPEAC	2008	DBLP DOI BibTeX RDF
2	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
2	Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll	Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP
2	Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor	Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.	SAMOS	2007	DBLP DOI BibTeX RDF
2	Jin Ho Ha, Jin Soo Kim, Myung Hoon Sunwoo	AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors.	SiPS	2007	DBLP DOI BibTeX RDF
2	Kang Zhao, Jinian Bian, Sheqin Dong	A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design.	CSCWD	2007	DBLP DOI BibTeX RDF
2	Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll	Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers.	ASAP	2007	DBLP DOI BibTeX RDF
2	David Montgomery, Ali Akoglu	Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications.	ASAP	2007	DBLP DOI BibTeX RDF
2	Koen Van Renterghem, P. Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu	Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow.	DATE	2007	DBLP DOI BibTeX RDF
2	Sung Dae Kim, Myung Hoon Sunwoo	Low Power ASIP Architecture Optimization based on Target Application Profiling.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna	Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.	ICESS	2007	DBLP DOI BibTeX RDF	DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs
2	Philip Brisk, Ajay K. Verma, Paolo Ienne	Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Hai Lin 0004, Yunsi Fei	Utilizing custom registers in application-specific instruction set processors for register spills elimination.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	custom register, ASIP, register file
2	Koen Van Renterghem, Dieter Verhulst, S. Verschuere, P. Demuytere, Jan Vandewege, Xing-Zhi Qiu	A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access.	FPL	2006	DBLP DOI BibTeX RDF
2	Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung Hoon Sunwoo	ASIP approach for implementation of H.264/AVC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Olivier Muller, Amer Baghdadi, Michel Jézéquel	ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.	DATE	2006	DBLP DOI BibTeX RDF
2	Daniele Lo Iacono, J. Zory, Ettore Messina, N. Piazzese, G. Saia, A. Bettinelli	ASIP architecture for multi-standard wireless terminals.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
2	Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	ASIP design and synthesis for non linear filtering in image processing.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
2	Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun	VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.	IIH-MSP	2006	DBLP DOI BibTeX RDF
2	Jianjun Guo, Kui Dai, Zhiying Wang	A High Performance Heterogeneous Architecture and Its Optimization Design.	HPCC	2006	DBLP DOI BibTeX RDF	SDTA, ASIP, Data Parallel
2	Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos	Automatic ADL-Based Assembler Generation for ASIP Programming Support.	SAMOS	2005	DBLP DOI BibTeX RDF
2	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
2	Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel	A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Integrated On-Chip Storage Evaluation in ASIP Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke	Automated data cache placement for embedded VLIW ASIPs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cache, ASIP, cache optimization, embedded applications
2	Seng Lin Shee, Sri Parameswaran, Newton Cheung	Novel architecture for loop acceleration: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration
2	Andreas Hoffmann, Frank Fiedler, Achim Nohl, Surender Parupalli	A Methodology and Tooling Enabling Application Specific Processor Design.	VLSI Design	2005	DBLP DOI BibTeX RDF	SIMD, VLIW, ASIP
2	Tim Good, Mohammed Benaissa	AES on FPGA from the Fastest to the Smallest.	CHES	2005	DBLP DOI BibTeX RDF	low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration
2	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.	SCOPES	2004	DBLP DOI BibTeX RDF
2	Yun Zhu, Xi Li, Yuchang Gong, Zhi-Gang Wang	PN-based Formal Modeling and Verification for ASIP Architecture.	ICESS	2004	DBLP DOI BibTeX RDF
2	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Exploring Storage Organization in ASIP Synthesis.	DSD	2003	DBLP DOI BibTeX RDF
2	Newton Cheung, Jörg Henkel, Sri Parameswaran	Rapid Configuration and Instruction Selection for an ASIP: A Case Study.	DATE	2003	DBLP DOI BibTeX RDF
2	Kurt Keutzer, Sharad Malik, A. Richard Newton	From ASIC to ASIP: The Next Design Discontinuity.	ICCD	2002	DBLP DOI BibTeX RDF	Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
2	T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua	Compiler-directed customization of ASIP cores.	CODES	2002	DBLP DOI BibTeX RDF	soft cores, embedded, customization, ASIP
2	Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr	Application specific compiler/architecture codesign: a case study.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	ASIP, architecture exploration, retargetable compiler
2	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
2	Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai	Effectiveness of the ASIP design system PEAS-III in design of pipelined processors.	ASP-DAC	2001	DBLP DOI BibTeX RDF
2	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	ASIP Design Methodologies : Survey and Issues.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Y. Bajot, H. Mehrez	Customizable DSP architecture for ASIP core design.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Evaluating register file size in ASIP design.	CODES	2001	DBLP DOI BibTeX RDF	instruction power model, synthesis, application specific instruction set processor, instruction set, register file, register spill
2	T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik	Processor Evaluation in an Embedded Systems Design Environment.	VLSI Design	2000	DBLP DOI BibTeX RDF	ASAP scheduler, Architecture constrained scheduler, ASIP, Processor architecture, Real-time constraints, Application profiling
2	William E. Dougherty, David J. Pursley, Donald E. Thomas	Subsetting Behavioral Intellectual Property for Low Power ASIP Design.	VLSI Signal Processing	1999	DBLP DOI BibTeX RDF
2	Young Geol Kim, Tag Gon Kim	A Design and Tool Reuse Methodology for Rapid Prototyping of Application Specific Instruction Set Processors. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Rapid prototyping, ASIP, Design reuse, Architecture description, Retargetable simulator
2	Andreas Pyttel, Alexander Sedlmeier, Christian Veith	PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems.	DATE	1998	DBLP DOI BibTeX RDF	FPGA, modular, statechart, application-specific
2	Luigi Raffo, Silvio P. Sabatini, M. Mantelli, A. De Gloria, Giacomo M. Bisio	Design of an ASIP architecture for low-level visual elaborations.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Stephanie Dogimont, M. Gumm, Friederich Mombers, Daniel Mlynek, A. Torielli	Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture.	ASAP	1997	DBLP DOI BibTeX RDF	RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller
2	Clifford Liem, Trevor C. May, Pierre G. Paulin	Register assignment through resource classification for ASIP microcode generation.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer	Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre	Loop Acceleration Exploration for ASIP Architecture.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer	Exploiting binary translation for fast ASIP design space exploration on FPGAs.	DATE	2012	DBLP BibTeX RDF
1	Antoine Trouve, Kazuaki Murakami	Augmenting DR-ASIP flexibility through multi-mode custom instructions.	SIGARCH Computer Architecture News	2011	DBLP DOI BibTeX RDF
1	Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume	A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Esther P. Adeva, Björn Mennenga, Gerhard Fettweis	Scalable ASIP implementation and parallelization of a MIMO sphere detector.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel	Area and throughput optimized ASIP for multi-standard turbo decoding.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Reza Faghih Mirzaee, Mohammad Eshghi	Design of an ASIP IDEA crypto processor.	NESEA	2011	DBLP DOI BibTeX RDF
1	Mariusz Grad, Christian Plessl	Just-in-Time Instruction Set Extension - Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel	A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding.	DATE	2011	DBLP DOI BibTeX RDF
1	Hee Kwan Eun, Sung Jo Hwang, Myung Hoon Sunwoo, Young Hwan Kim, Hi-Seok Kim	Integer-pel Motion Estimation specific instructions and their hardware architecture for ASIP.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Simon Rajotte, Diana Carolina Gil, J. M. Pierre Langlois	Combining ISA extensions and subsetting for improved ASIP performance and cost.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Hanan M. Hassan, Ahmed F. Shalash, Karim Mohamed	FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao	An ultra-fast hybrid simulation framework for ASIP.	ICECS	2011	DBLP DOI BibTeX RDF
1	Zdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár	Fast just-in-time translated simulator for ASIP design.	DDECS	2011	DBLP DOI BibTeX RDF
1	Hong Chinh Doan, Haris Javaid, Sri Parameswaran	Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos.	ESTImedia	2011	DBLP DOI BibTeX RDF
1	Fethi Tlili, Akram Ghorbel	ASIP Solution for Implementation of H.264 Multi Resolution Motion Estimation.	IJCNS	2010	DBLP DOI BibTeX RDF
1	Götz Kappen, Lothor Kurz, O. Priebe, Tobias G. Noll	Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Matthias Alles, Timo Vogt, Christian Brehm, Norbert Wehn	FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	E. Tasdemir, Götz Kappen, Tobias G. Noll	Potential of using block floating point arithmetic in ASIP-based GNSS-receivers.	ASAP	2010	DBLP DOI BibTeX RDF
1	Ioanna Tsekoura, Georgios N. Selimis, Jos Hulzink, Francky Catthoor, Jos Huisken, Harmke de Groot, Constantinos E. Goutis	Exploration of cryptographic ASIP designs for wireless sensor nodes.	ICECS	2010	DBLP DOI BibTeX RDF
1	David Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor	Exploiting finite precision information to guide data-flow mapping.	DAC	2010	DBLP DOI BibTeX RDF	finite precision, mapping efficiency, ASIP
1	Andreas Loos, Michael Schmidt, Dietmar Fey, Jens Grobel	Dynamically Programmable Image Processor for Compact Vision Systems.	CIT	2010	DBLP DOI BibTeX RDF	Embedded image processors, dynamically programmable ASIP
1	Per Karlström, Wenbiao Zhou, Dake Liu	Operation Classification for Control Path Synthetization with NoGAP.	ITNG	2010	DBLP DOI BibTeX RDF	Control path, CAD, Pipelining, ADL, ASIP, RTL
1	Hai Lin 0004, Yunsi Fei	Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives.	ISLPED	2010	DBLP DOI BibTeX RDF	asips, multi-objective design
1	David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr	Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.	IACR Cryptology ePrint Archive	2009	DBLP BibTeX RDF
1	Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel	ASIP-Based Universal Demapper for Multiwireless Standards.	Embedded Systems Letters	2009	DBLP DOI BibTeX RDF
1	Olivier Muller, Amer Baghdadi, Michel Jézéquel	From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel	Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer.	IEEE International Workshop on Rapid System Prototyping	2009	DBLP DOI BibTeX RDF
1	Praveen Raghavan, Francky Catthoor	Register file exploration for a multi-standard wireless forward error correction ASIP.	SiPS	2009	DBLP DOI BibTeX RDF
1	Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.	ASAP	2009	DBLP DOI BibTeX RDF
1	Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel	ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.	DATE	2009	DBLP BibTeX RDF
1	Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger	A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing.	DATE	2009	DBLP BibTeX RDF
1	Steffen Kunze, Emil Matús, Gerhard Fettweis	ASIP Decoder Architecture for Convolutional and LDPC Codes.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid	Task management in MPSoCs: An ASIP approach.	ICCAD	2009	DBLP BibTeX RDF