Search results for "ASP-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu	Voltage island-driven floorplanning considering level shifter placement.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Shao-Yi Chien, Teng-Yuan Cheng, Chieh-Chuan Chiu, Pei-Kuei Tsung, Chia-han Lee, V. Srinivasa Somayazulu, Yen-Kuang Chen	Power optimization of wireless video sensor nodes in M2M networks.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng	A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1		Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012	ASP-DAC	2012	DBLP BibTeX RDF
1	Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou	Thread affinity mapping for irregular data access on shared Cache GPGPU.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yavuz Yetim, Sharad Malik, Margaret Martonosi	EPROF: An energy/performance/reliability optimization framework for streaming applications.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh	Selective time borrowing for DSP pipelines with hybrid voltage control loop.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yang Shang, Wei Fei, Hao Yu	Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Khalid Latif 0002, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman	Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yi-Chung Chen, Wei Zhang, Hai Li	A Look Up Table design with 3D bipolar RRAMs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi	A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xiang Chen, Jian Zheng, Yiran Chen, Wei Zhang, Hai Li	Fine-grained dynamic voltage scaling on OLED display.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Parisa Razaghi, Andreas Gerstlauer	Automatic timing granularity adjustment for host-compiled software simulation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa	A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	Engineering complex systems for health, security and the environment.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Bijan Alizadeh	A formal approach to debug polynomial datapath designs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Borislav Alexandrov, Owen Sullivan, Satish Kumar, Saibal Mukhopadhyay	Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May	Hardware prototyping of novel invasive multicore architectures.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Amir Nahir, Avi Ziv, Subrat Panda	Optimizing test-generation to the execution platform.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Mohammad Abdur Rouf, Soontae Kim	Low-cost control flow error protection by exploiting available redundancies in the pipeline.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Qing Xie, Yanzhi Wang, Massoud Pedram, Younghyun Kim, Donghwa Shin, Naehyuck Chang	Charge replacement in hybrid electrical energy storage systems.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai	Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yang Song, Guoyong Shi	Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jayanand Asok Kumar, Shobha Vasudevan	Verifying dynamic power management schemes using statistical model checking.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xiaoming Chen, Yu Wang, Huazhong Yang	An adaptive LU factorization algorithm for parallel circuit simulation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang	Clock rescheduling for timing engineering change orders.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham	Character design and stamp algorithms for Character Projection Electron-Beam Lithography.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen	Micro-bump assignment for 3D ICs using order relation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Hiroaki Yoshida	Post-silicon patching for verification/debugging with high-level models and programmable logic.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Marisha Rawlins, Ann Gordon-Ross	An application classification guided cache tuning heuristic for multi-core architectures.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ravi Iyer	Accelerator-rich architectures: Implications, opportunities and challenges.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera	A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang	Post silicon skew tuning: Survey and analysis.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Qiang Xu, Li Jiang, Huiyun Li, Bill Eklow	Yield enhancement for 3D-stacked ICs: Recent advances and challenges.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Keisuke Inoue, Mineo Kaneko	Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang	Design for manufacturability and reliability for TSV-based 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Shuangchen Li, Yongpan Liu, Daming Zhang, Xinyu He, Pei Zhang, Huazhong Yang	A hierarchical C2RTL framework for FIFO-connected stream applications.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Duo Ding, Bei Yu, David Z. Pan	GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Kiyoung Kim, Taewhan Kim	Algorithm for synthesizing design context-aware fast carry-skip adders.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Tianzheng Wang, Duo Liu, Zili Shao, Chengmo Yang	Write-activity-aware page table management for PCM-based embedded systems.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Shuta Kimura, Masanori Hashimoto, Takao Onoye	Body bias clustering for low test-cost post-silicon tuning.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xuexin Liu, Sheldon X.-D. Tan, Zhigang Hao, Guoyong Shi	Time-domain performance bound analysis of analog circuits considering process variations.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra	An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Miroslav N. Velev, Ping Gao 0002	Automated debugging of counterexamples in formal verification of pipelined microprocessors.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Leandro Fiorin, Alberto Ferrante, Konstantinos Padarnitsas, Francesco Regazzoni	Security Enhanced Linux on embedded systems: A hardware-accelerated implementation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan	EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Aritra Hazra, Pallab Dasgupta, Ansuman Banerjee, Kevin Harer	Formal methods for coverage analysis of architectural power states in power-managed designs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Shihheng Tsai, Man-Yu Li, Chung-Yang Huang	A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Wolfgang Müller 0003, Markus Becker, Ahmed Elfeky, Anthony DiPasquale	Virtual prototyping of Cyber-Physical Systems.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Subhasish Mitra, David Lin, Nagib Hakim, Donald S. Gardner	Bug localization techniques for effective post-silicon validation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Dae Sung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yen-Kuang Chen	Challenges and opportunities of internet of things.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen	A fast thermal aware placement with accurate thermal analysis based on Green function.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yukihide Kohira, Atsushi Takahashi	An any-angle routing method using quasi-Newton method.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Martin Lukasiewycz, Reinhard Schneider, Dip Goswami, Samarjit Chakraborty	Modular scheduling of distributed heterogeneous time-triggered automotive systems.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xin Zhao, Sung Kyu Lim	Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang 0001, Bin Liu 0006, Raghu Prabhakar, Glenn Reinman, Marco Vitanza	Compilation and architecture support for customized vector instruction extension.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita	Automated data analysis techniques for a modern silicon debug environment.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin	Crosstalk-aware power optimization with multi-bit flip-flops.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Wei Liu, Xiaotian Fei, Tao Tang, Pengjun Wang, Hong Luo, Beixing Deng, Huazhong Yang	Application specific sensor node architecture optimization - Experiences from field deployments.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Dukyoung Yun, Sungchan Kim, Soonhoi Ha	Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Saket Gupta, Sachin S. Sapatnekar	GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang	Memory access aware power gating for MPSoCs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Weiwei Chen, Rainer Dömer	An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao	An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Dimin Niu, Yang Xiao, Yuan Xie	Low power memristor-based ReRAM design with Error Correcting Code.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye	Fast floating random walk algorithm formulti-dielectric capacitance extraction with numerical characterization of Green's functions.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Li Li, Yinghai Lu, Hai Zhou	Optimal prescribed-domain clock skew scheduling.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jing Xie, Yu Wang, Yuan Xie	Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda	Simultaneous data and power transmission using nested clover coils.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jianxin Fang, Sachin S. Sapatnekar	The impact of hot carriers on timing in large circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng	A 60mW baseband SoC for CMMB receiver.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh	Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hailong Yao, Yici Cai, Qiang Gao	LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan	A reconfigurable platform for the design and verification of domain-specific accelerators.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Peter Lisherness, Kwang-Ting Cheng	Improving validation coverage metrics to account for limited observability.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jagdish Sabarad, Srinidhi Kestur, Sun-Mi Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla	A reconfigurable accelerator for neuromorphic object recognition.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Omid Sarbishei, Katarzyna Radecka	Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Mike O'Connor	Accelerated processing and the Fusion System Architecture.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jinho Lee, Kiyoung Choi	Memory-aware mapping and scheduling of tasks and communications on many-core SoC.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu	Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita	On error tolerance and Engineering Change with Partially Programmable Circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu	ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jinglei Wang, Dongsheng Wang, Haixia Wang, Yibo Xue	Dynamic reusability-based replication with network address mapping in CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hany Kashif, Hiren D. Patel, Sebastian Fischmeister	Using link-level latency analysis for path selection for real-time communication on NoCs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu	Energy-efficient RISC design with on-demand circuit-level timing speculation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho	An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	Crosstalk-aware statistical interconnect delay calculation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou	Platform characterization for Domain-Specific Computing.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jörg Henkel	RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Pei-Yu Huang, Yu-Min Lee, Chi-Wen Pan	On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniques.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie	Thermal-aware power network design for IR drop reduction in 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Vivek Joshi, Kanak Agarwal, Dennis Sylvester	Design-patterning co-optimization of SRAM robustness for double patterning lithography.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou	On error modeling of electrical bugs for post-silicon timing validation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan	When to forget: A system-level perspective on STT-RAMs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ahmed Musa, Kenichi Okada, Akira Matsuzawa	A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Rong Ye, Qiang Xu	Learning-based power management for multi-core processors via idle period manipulation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yuko Hara, Hiroyuki Tomiyama	Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis.	ASP-DAC	2012	DBLP DOI BibTeX RDF

Publications at "ASP-DAC"( http://dblp.L3S.de/Venues/ASP-DAC )