Search results for "ASP-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Hidetoshi Onodera	Dependable VLSI Platform using Robust Fabrics.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yun Liang, Zheng Cui, Kyle Rupnow, Deming Chen	Register and thread structure optimization for GPUs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi	Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai	Performance bound and yield analysis for analog circuits under process variations.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi	Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato	Realization of frequency-domain circuit analysis through random walk.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Nikhil A. Patil, Derek Chiou	Implementing microprocessors from simplified descriptions.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa	DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto	A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, Sung Kyu Lim	Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori	Statistical analysis of BTI in the presence of process-induced voltage and temperature variations.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yazhi Huang, Mengying Zhao, Chun Jason Xue	WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann	Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Mirela Alistar, Paul Pop, Jan Madsen	Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Qing Xie, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, Naehyuck Chang	An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Pei-Ci Wu, Qiang Ma 0002, Martin D. F. Wong	An ILP-based automatic bus planner for dense PCBs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang	HS3DPG: Hierarchical simulation for 3D P/G network.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi	Deflection routing in 3D Network-on-Chip with TSV serialization.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou	Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Junichi Fujikata, Masataka Noguchi, Makoto Miura, Masashi Takahashi, Shigeki Takahashi, Tsuyoshi Horikawa, Yutaka Urino, Takahiro Nakamura, Yasuhiko Arakawa	High performance PIN Ge photodetector and Si optical modulator with MOS junction for photonics-electronics convergence system.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shinya Tokunaga	2.5D design methodology.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Mian Muhammad Hamayun, Frédéric Pétrot, Nicolas Fournel	Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai	I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Stefan Hougardy, Tim Nieberg, Jan Schneider	BonnCell: Automatic layout of leaf cells.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A case for wireless 3D NoCs for CMPs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen	A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim	Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Qing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yiran Chen, Yanxiang He	Compiler-assisted refresh minimization for volatile STT-RAM cache.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Hehua Zhang, Yu Jiang, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun	Sequential dependency and reliability analysis of embedded systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi	Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Sangmin Kim, Duckhwan Kim, Youngsoo Shin	Pulsed-latch ASIC synthesis in industrial design flow.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Kent W. Nixon, Xiang Chen, Zhi-Hong Mao, Yiran Chen, Kang Li	Mobile user classification and authorization based on gesture usage recognition.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Sebastian Reiter, Michael Pressler, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel	Reliability assessment of safety-relevant automotive systems in a model-based design flow.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Mohammed El-Shambakey, Binoy Ravindran	On real-time STM concurrency control for embedded software with improved schedulability.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Mian Dong, Po-Hsiang Lai, Zhu Li	Can we identify smartphone app by power trace? [Extended abstract for special session].	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty	Schedule integration for time-triggered systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao	Symmetrical buffered clock-tree synthesis with supply-voltage alignment.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler	Improving the mapping of reversible circuits to quantum circuits using multiple target lines.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim	High-density integration of functional modules using monolithic 3D-IC technology.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Tadatoshi Sekine, Hideki Asai	Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Li Yu, Omar Mysore, Lan Wei, Luca Daniel, Dimitri A. Antoniadis, Ibrahim M. Elfadel, Duane S. Boning	An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi	Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Baris Arslan, Alex Orailoglu	Full exploitation of process variation space for continuous delivery of optimal delay test quality.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shunta Iguchi, Akira Saito, Kentaro Honda, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya	315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yang Song, Haipeng Fu, Hao Yu, Guoyong Shi	Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Pei-Ci Wu, Martin D. F. Wong	Network flow modeling for escape routing on staggered pin arrays.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Louis Y.-Z. Lin, Christina C.-H. Liao, Charles H.-P. Wen	Synthesizing multiple scan chains by cost-driven spectral ordering.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Bernard Schmidt, Carlos Villarraga, Jörg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz	A computational model for SAT-based verification of hardware-dependent low-level embedded system software.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Muhammad Umer Farooq, Likun Xia	Local approximation improvement of trajectory piecewise linear macromodels through Chebyshev interpolating polynomials.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Wajid Hassan Minhass, Paul Pop, Jan Madsen, Tsung-Yi Ho	Control synthesis for the flow-based microfluidic large-scale integration biochips.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Huping Ding, Yun Liang, Tulika Mitra	Shared cache aware task mapping for WCRT minimization.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Joohee Kim, Joungho Kim	Signal integrity modeling and measurement of TSV in 3D IC.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Swathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen	High-level synthesis of multiple dependent CUDA kernels on FPGA.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho	A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen	Loadsa: A yield-driven top-down design method for STT-RAM array.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki	Hardware security strategies exploiting nanoelectronic circuits.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu	Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Kenta Sogo, Akihiro Toya, Takamaro Kikkawa	A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King	ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Bei Yu, Jhih-Rong Gao, David Z. Pan	L-shape based layout fracturing for e-beam lithography.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne	Design issues in heterogeneous 3D/2.5D integration.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao	Optimizing routability in large-scale mixed-size placement.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Peter De Dobbelaere	Silicon photonics technology platform for embedded and integrated optical interconnect systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yuko Hara-Azumi, Takuya Azumi, Nikil D. Dutt	VISA synthesis: Variation-aware Instruction Set Architecture synthesis.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Mohammad H. Foroozannejad, Brent Bohnenstiehl, Soheil Ghiasi	BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Bin Xue, Prosenjit Chatterjee, Sandeep K. Shukla	Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	M. Kondo, S. T. Nguyen, T. Hirao, T. Soga, H. Sasaki, K. Inoue	SMYLEref: A reference architecture for manycore-processor SoCs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yang Zhang, Neric Fong, Ngai Wong	Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin	A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Duo Liu, Tianzheng Wang, Yi Wang, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Di Zhu, Yanzhi Wang, Siyu Yue, Qing Xie, Massoud Pedram, Naehyuck Chang	Maximizing return on investment of a grid-connected hybrid electrical energy storage system.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yuri Ardila, Natsuki Kawai, Takashi Nakamura, Yosuke Tamura	Support tools for porting legacy applications to multicore.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jungmoon Kim, Chulwoo Kim	A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Kan Wang, Sheqin Dong	Power optimization for application-specific 3D network-on-chip with multiple supply voltages.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jörg Henkel, Thomas Ebi, Hussam Amrouch, Heba Khdr	Thermal management for dependable on-chip systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Matthias Kauer, Sebastian Steinhorst, Dip Goswami, Reinhard Schneider, Martin Lukasiewycz, Samarjit Chakraborty	Formal verification of distributed controllers using Time-Stamped Event Count Automata.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Koji Inoue	SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi	A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun	Heterogeneous memory management for 3D-DRAM and external DRAM with QoS.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto	A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Kazuya Masu, Noboru Ishihara, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi	Challenges in integration of diverse functionalities on CMOS.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong	VFCC: A verification framework of cache coherence using parallel simulation.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Wei Zhao, Yici Cai, Jianlei Yang	A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Zao Liu, Tailong Xu, Sheldon X.-D. Tan, Hai Wang	Dynamic thermal management for multi-core microprocessors considering transient thermal effects.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Hiroyuki Tomiyama, Takuji Hieda, Naoki Nishiyama, Noriko Etani, Ittetsu Taniguchi	SMYLE OpenCL: A programming framework for embedded many-core SoCs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1		18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013	ASP-DAC	2013	DBLP BibTeX RDF
1	Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Zao Liu, Sheldon X.-D. Tan, Hai Wang, Sahana Swarup, Ashish Gupta 0007	Compact nonlinear thermal modeling of packaged integrated systems.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Qing Wan, Hui Wu, Jingling Xue	Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Mojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori	CLASS: Combined logic and architectural soft error sensitivity analysis.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng	Layer minimization in escape routing for staggered-pin-array PCBs.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Haris Javaid, Daniel Witono, Sri Parameswaran	Multi-mode pipelined MPSoCs for streaming applications.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yukoh Matsumoto, Hiroyuki Uchida, Michiya Hagimoto, Yasumori Hibi, Sunao Torii, Masamichi Izumida	Manycore processor for video mining applications.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Su Myat Min, Haris Javaid, Sri Parameswaran	RExCache: Rapid exploration of unified last-level cache.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu	Power distribution network modeling for 3-D ICs with TSV arrays.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, Heiko Falk	Real-time partitioned scheduling on multi-core systems with local and global memories.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Youngjoo Lee, Hoyoung Yoo, In-Cheol Park	A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Yuelin Du, Hongbo Zhang, Qiang Ma 0002, Martin D. F. Wong	Linear time algorithm to find all relocation positions for EUV defect mitigation.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Jiwu Shu, Zhirong Shen, Wei Xue, Yingxun Fu	Secure storage system and key technologies.	ASP-DAC	2013	DBLP DOI BibTeX RDF
1	Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi	Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.	ASP-DAC	2013	DBLP DOI BibTeX RDF

Publications at "ASP-DAC"( http://dblp.L3S.de/Venues/ASP-DAC )