Search results for "ASYNC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jo C. Ebergen, Bill Coates, Austin Lee	Long-Distance On-chip Communication Using GasP.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Nabil Imam, Rajit Manohar	Address-Event Communication Using Token-Ring Mutual Exclusion.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Xuefu Zhang, Delong Shang, Fei Xia, Alexandre Yakovlev	A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Victor Khomenko	Logic Decomposition of Asynchronous Circuits Using STG Unfoldings.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Evriklis Kounalakis, Christos P. Sotiriou	CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Xin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass	GALS Design for On-chip Ground Bounce Suppression.	ASYNC	2011	DBLP DOI BibTeX RDF
1		17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011, Cornell University, Ithaca, New York, USA, 27-29 April 2011	ASYNC	2011	DBLP BibTeX RDF
1	Masashi Imai, Tomohiro Yoneda	Improving Dependability and Performance of Fully Asynchronous On-chip Networks.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Nikolaos Andrikos, Luciano Lavagno	Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Suwen Yang, Ian W. Jones, Mark R. Greenstreet	Synchronizer Performance in Deep Sub-Micron Technology.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev	Variation Tolerant AFPGA Architecture.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory	Formal Verification of C-element Circuits.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Carlos Ortega, Jonathan Tse, Rajit Manohar	Static Power Reduction Techniques for Asynchronous Circuits.	ASYNC	2010	DBLP DOI BibTeX RDF
1		16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010	ASYNC	2010	DBLP BibTeX RDF
1	Christopher LaFrieda, Benjamin Hill, Rajit Manohar	An Asynchronous FPGA with Two-Phase Enable-Scaled Routing.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Santosh N. Varanasi, Kenneth S. Stevens, Graham M. Birtwistle	Concurrency Reduction of Untimed Latch Protocols - Theory and Practice.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Florent Ouchet, Katell Morin-Allory, Laurent Fesquet	Delay Insensitivity Does Not Mean Slope Insensitivity!	ASYNC	2010	DBLP DOI BibTeX RDF
1	Ad M. G. Peeters, Frank te Beest, Mark de Wit, Willem C. Mallon	Click Elements: An Implementation Style for Data-Driven Compilation.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Basit Riaz Sheikh, Rajit Manohar	An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny	The Devolution of Synchronizers.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Nicolas Leblond, Pascal Vivet, G. Waltisperger, Jérôme Willemin	Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Gennette Gill, Montek Singh	Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Chao Yan, Mark R. Greenstreet, Jochen Eisinger	Formal Verification of an Arbiter Circuit.	ASYNC	2010	DBLP DOI BibTeX RDF
1	John Hansen, Montek Singh	A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken, Gordon Russell	Extending Synchronization from Super-Threshold to Sub-threshold Region.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Mario R. Casu	Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming.	ASYNC	2010	DBLP DOI BibTeX RDF
1	William J. Dally, Stephen G. Tell	The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Swetha Mettala Gilla, Marly Roncken, Ivan Sutherland	Long-Range GasP with Charge Relaxation.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.	ASYNC	2010	DBLP DOI BibTeX RDF
1	W. B. Toms, David A. Edwards	M-of-N Code Decomposition for Indicating Combinational Logic.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev	Delay/Phase Regeneration Circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel	Design of a High-Speed Asynchronous Turbo Decoder.	ASYNC	2007	DBLP DOI BibTeX RDF
1		13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA	ASYNC	2007	DBLP BibTeX RDF
1	Mark B. Josephs	Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Andrew Lines	The Vortex: A Superscalar Asynchronous Processor.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Steve Furber, Arash Saifhashemi	Notes On Pulse Signaling.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Wade L. Williams, Philip E. Madrid, Scott C. Johnson	Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Amitava Mitra, William F. McLaughlin, Steven M. Nowick	Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener	The Design of a Genetic Muller C-Element.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Suwen Yang, Mark R. Greenstreet, Jihong Ren	A Jitter Attenuating Timing Chain.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Alex Chow, William S. Coates, David Hopkins	A Configurable Asynchronous Pseudorandom Bit Sequence Generator.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Robert D. Mullins, Simon W. Moore	Demystifying Data-Driven and Pausible Clocking Schemes.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet	Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Melinda Y. Agyekum, Steven M. Nowick	A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein	Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell	A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks	On-chip samplers for test and debug of asynchronous circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan	Interface Design for Rationally Clocked GALS Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Song Peng, Rajit Manohar	Self-Healing Asynchronous Arrays.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Nobuo Karaki	Asynchronous Design: An Enabler for Flexible Microelectronics.	ASYNC	2006	DBLP DOI BibTeX RDF
1	D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin	AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Edith Beigné, Pascal Vivet	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
1	David Kinniment, Keith Heron, Gordon Russell	Measuring Deep Metastability.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies	Slack Matching Asynchronous Designs.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Cheoljoo Jeong, Steven M. Nowick	Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	ASYNC	2006	DBLP DOI BibTeX RDF
1	W. B. Toms, David A. Edwards, Andrew Bardsley	Synthesising Heterogeneously Encoded Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet, Jihong Ren	Surfing Interconnect.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Jean-Pierre Schoellkopf	ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
1	L. Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago	An ultra-low energy asynchronous processor for Wireless Sensor Networks.	ASYNC	2006	DBLP DOI BibTeX RDF	lowenergy, low EMI, AVR CPU, Wireless sensor networks, low-power, desynchronization
1	Piyush Prakash, Alain J. Martin	Slack Matching Quasi Delay-Insensitive Circuits.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Alex Chow, Bill Coates, Justin Schauer, David Hopkins	An Asynchronous High-Throughput Control Circuit For Proximity Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel	A Level-Crossing Flash Asynchronous Analog-to-Digital Converter.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner	GALS at ETH Zurich: Success or Failure.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Feng Shi, Yiorgos Makris	A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Masashi Imai, Takashi Nanya	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.	ASYNC	2006	DBLP DOI BibTeX RDF
1		12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France	ASYNC	2006	DBLP BibTeX RDF
1	Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Yiorgos Makris	Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Ferdinand Peper	Asynchronous Architectures for Nanometer Scales.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Oleg V. Maevsky	Multiple-Rail Phase-Encoding for NoC.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Frederic Worm, Patrick Thiran, Paolo Ienne	A Unified Coding Framework for Delay-Insensitivity.	ASYNC	2005	DBLP DOI BibTeX RDF
1		11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA	ASYNC	2005	DBLP BibTeX RDF
1	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar	An Asynchronous Router for Multiple Service Levels Networks on Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Robert P. Colwell	Deep Pipelines vs. Risk and Power Walls.	ASYNC	2005	DBLP BibTeX RDF
1	Suwen Yang, Brian D. Winters, Mark R. Greenstreet	Energy Efficient Surfing.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Milos Krstic, Eckhard Grass, Christian Stahl	Request-Driven GALS Technique for Wireless Communication System.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Frank te Beest, Ad M. G. Peeters	A Multiplexor Based Test Method for Self-Timed Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Vassilis Zebilis, Christos P. Sotiriou	Controlling Event Spacing in Self-Timed Rings.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar	BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Phillip Restle, Kenneth L. Shepard	New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems.	ASYNC	2005	DBLP BibTeX RDF
1	Joep L. W. Kessels	Register Communication between Mutually Asynchronous Domains.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Tin Wai Kwan, Maitham Shams	Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald	Delay Insensitive Encoding and Power Analysis: A Balancing Act.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland	GasP Control for Domino Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Scott Fairbanks, Simon W. Moore	Self-Timed Circuitry for Global Clocking.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Nikolai Starodoubtsev, Sergei Bystrov	Behavior and Synthesis of Two-Input Gate Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Robert J. Drost, Ivan E. Sutherland	Proximity Communication and Time.	ASYNC	2005	DBLP BibTeX RDF
1	Justin Hensley, Anselmo Lastra, Montek Singh	A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers	High Level Synthesis of Timed Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens	Modeling and Verifying Circuits Using Generalized Relative Timing.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Tobias Bjerregaard, Jens Sparsø	A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Wonjin Jang, Alain J. Martin	SEU-Tolerant QDI Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Yee William Li, Kenneth L. Shepard, Yannis P. Tsividis	Continuous-Time Digital Signal Processors.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou	Handshake Protocols for De-Synchronization.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Radu Negulescu	General Testers for Asynchronous Circuits.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Christer Svensson	Synchronous Latency Insensitive Design. (PDF / PS)	ASYNC	2004	DBLP DOI BibTeX RDF

Publications at "ASYNC"( http://dblp.L3S.de/Venues/ASYNC )