Search results for "ASYNC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jens Sparsø, Montek Singh, Pascal Vivet (eds.)	18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012	ASYNC	2012	DBLP BibTeX RDF
1	John Hansen, Montek Singh	A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous Systems.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Andrey Mokhov, Danil Sokolov, Alex Yakovlev	Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Ney Calazans, Pascal Vivet	Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Tsung-Te Liu, Jan M. Rabaey	Statistical Analysis and Optimization of Asynchronous Digital Circuits.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha	A Digital Neurosynaptic Core Using Event-Driven QDI Circuits.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana	An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu	High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Marco Cannizzaro, Luciano Lavagno	PID (Partial Inversion Data): An M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global Communication.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Robert B. Reese, Scott C. Smith, Mitchell A. Thornton	Uncle - An RTL Approach to Asynchronous Design.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Basit Riaz Sheikh, Rajit Manohar	An Asynchronous Floating-Point Multiplier.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Xin Fan, Milos Krstic, Eckhard Grass	Performance Analysis of GALS Datalink Based on Pausible Clocking.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Jiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens	Ultra Low Power Booth Multiplier Using Asynchronous Logic.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Navaneeth Jamadagni, Jo C. Ebergen	An Asynchronous Divider Implementation.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Yvain Thonnart, Edith Beigné, Pascal Vivet	A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Michel Laurence	Introduction to Octasic Asynchronous Processor Technology.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Benjamin Tang, Stephen Longfield Jr., Sunil A. Bhave, Rajit Manohar	A Low Power Asynchronous GPS Baseband Processor.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Marc Renaudin, Alain Fonkoua	Tiempo Asynchronous Circuits System Verilog Modeling Language.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Mehrdad Najibi, Peter A. Beerel	Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Manoj K. Yadav, Mario R. Casu, Maurizio Zamboni	DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems.	ASYNC	2012	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Bill Coates, Austin Lee	Long-Distance On-chip Communication Using GasP.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Nabil Imam, Rajit Manohar	Address-Event Communication Using Token-Ring Mutual Exclusion.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Xuefu Zhang, Delong Shang, Fei Xia, Alexandre Yakovlev	A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Victor Khomenko	Logic Decomposition of Asynchronous Circuits Using STG Unfoldings.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Evriklis Kounalakis, Christos P. Sotiriou	CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Xin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass	GALS Design for On-chip Ground Bounce Suppression.	ASYNC	2011	DBLP DOI BibTeX RDF
1		17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011, Cornell University, Ithaca, New York, USA, 27-29 April 2011	ASYNC	2011	DBLP BibTeX RDF
1	Masashi Imai, Tomohiro Yoneda	Improving Dependability and Performance of Fully Asynchronous On-chip Networks.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Nikolaos Andrikos, Luciano Lavagno	Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Suwen Yang, Ian W. Jones, Mark R. Greenstreet	Synchronizer Performance in Deep Sub-Micron Technology.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev	Variation Tolerant AFPGA Architecture.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory	Formal Verification of C-element Circuits.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar	Static Power Reduction Techniques for Asynchronous Circuits.	ASYNC	2010	DBLP DOI BibTeX RDF
1		16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010	ASYNC	2010	DBLP BibTeX RDF
1	Christopher LaFrieda, Benjamin Hill, Rajit Manohar	An Asynchronous FPGA with Two-Phase Enable-Scaled Routing.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Santosh N. Varanasi, Kenneth S. Stevens, Graham M. Birtwistle	Concurrency Reduction of Untimed Latch Protocols - Theory and Practice.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Florent Ouchet, Katell Morin-Allory, Laurent Fesquet	Delay Insensitivity Does Not Mean Slope Insensitivity!	ASYNC	2010	DBLP DOI BibTeX RDF
1	Ad M. G. Peeters, Frank te Beest, Mark de Wit, Willem C. Mallon	Click Elements: An Implementation Style for Data-Driven Compilation.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Basit Riaz Sheikh, Rajit Manohar	An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny	The Devolution of Synchronizers.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Nicolas Leblond, Pascal Vivet, G. Waltisperger, Jérôme Willemin	Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Gennette Gill, Montek Singh	Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Chao Yan, Mark R. Greenstreet, Jochen Eisinger	Formal Verification of an Arbiter Circuit.	ASYNC	2010	DBLP DOI BibTeX RDF
1	John Hansen, Montek Singh	A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken, Gordon Russell	Extending Synchronization from Super-Threshold to Sub-threshold Region.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Mario R. Casu	Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming.	ASYNC	2010	DBLP DOI BibTeX RDF
1	William J. Dally, Stephen G. Tell	The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Swetha Mettala Gilla, Marly Roncken, Ivan Sutherland	Long-Range GasP with Charge Relaxation.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.	ASYNC	2010	DBLP DOI BibTeX RDF
1	W. B. Toms, David A. Edwards	M-of-N Code Decomposition for Indicating Combinational Logic.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev	Delay/Phase Regeneration Circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel	Design of a High-Speed Asynchronous Turbo Decoder.	ASYNC	2007	DBLP DOI BibTeX RDF
1		13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA	ASYNC	2007	DBLP BibTeX RDF
1	Mark B. Josephs	Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Andrew Lines	The Vortex: A Superscalar Asynchronous Processor.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Steve Furber, Arash Saifhashemi	Notes On Pulse Signaling.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Wade L. Williams, Philip E. Madrid, Scott C. Johnson	Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Amitava Mitra, William F. McLaughlin, Steven M. Nowick	Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener	The Design of a Genetic Muller C-Element.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Suwen Yang, Mark R. Greenstreet, Jihong Ren	A Jitter Attenuating Timing Chain.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Alex Chow, William S. Coates, David Hopkins	A Configurable Asynchronous Pseudorandom Bit Sequence Generator.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Robert D. Mullins, Simon W. Moore	Demystifying Data-Driven and Pausible Clocking Schemes.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet	Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Melinda Y. Agyekum, Steven M. Nowick	A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein	Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell	A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks	On-chip samplers for test and debug of asynchronous circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan	Interface Design for Rationally Clocked GALS Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Song Peng, Rajit Manohar	Self-Healing Asynchronous Arrays.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Nobuo Karaki	Asynchronous Design: An Enabler for Flexible Microelectronics.	ASYNC	2006	DBLP DOI BibTeX RDF
1	D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin	AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Edith Beigné, Pascal Vivet	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
1	David Kinniment, Keith Heron, Gordon Russell	Measuring Deep Metastability.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies	Slack Matching Asynchronous Designs.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Cheoljoo Jeong, Steven M. Nowick	Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	ASYNC	2006	DBLP DOI BibTeX RDF
1	W. B. Toms, David A. Edwards, Andrew Bardsley	Synthesising Heterogeneously Encoded Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet, Jihong Ren	Surfing Interconnect.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Jean-Pierre Schoellkopf	ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
1	L. Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago	An ultra-low energy asynchronous processor for Wireless Sensor Networks.	ASYNC	2006	DBLP DOI BibTeX RDF	lowenergy, low EMI, AVR CPU, Wireless sensor networks, low-power, desynchronization
1	Piyush Prakash, Alain J. Martin	Slack Matching Quasi Delay-Insensitive Circuits.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Alex Chow, Bill Coates, Justin Schauer, David Hopkins	An Asynchronous High-Throughput Control Circuit For Proximity Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel	A Level-Crossing Flash Asynchronous Analog-to-Digital Converter.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner	GALS at ETH Zurich: Success or Failure.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Feng Shi, Yiorgos Makris	A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Masashi Imai, Takashi Nanya	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.	ASYNC	2006	DBLP DOI BibTeX RDF
1		12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France	ASYNC	2006	DBLP BibTeX RDF
1	Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Yiorgos Makris	Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Ferdinand Peper	Asynchronous Architectures for Nanometer Scales.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Oleg V. Maevsky	Multiple-Rail Phase-Encoding for NoC.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Frederic Worm, Patrick Thiran, Paolo Ienne	A Unified Coding Framework for Delay-Insensitivity.	ASYNC	2005	DBLP DOI BibTeX RDF
1		11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA	ASYNC	2005	DBLP BibTeX RDF
1	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar	An Asynchronous Router for Multiple Service Levels Networks on Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Robert P. Colwell	Deep Pipelines vs. Risk and Power Walls.	ASYNC	2005	DBLP BibTeX RDF
1	Suwen Yang, Brian D. Winters, Mark R. Greenstreet	Energy Efficient Surfing.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Milos Krstic, Eckhard Grass, Christian Stahl	Request-Driven GALS Technique for Wireless Communication System.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Frank te Beest, Ad M. G. Peeters	A Multiplexor Based Test Method for Self-Timed Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF

Publications at "ASYNC"( http://dblp.L3S.de/Venues/ASYNC )