Search results for "Aarti Gupta"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jing Yang, Gogul Balakrishnan, Naoto Maeda, Franjo Ivancic, Aarti Gupta, Nishant Sinha, Sriram Sankaranarayanan, Naveen Sharma	Object Model Construction for Inheritance in C++ and Its Applications to Program Analysis.	CC	2012	DBLP DOI BibTeX RDF
1	Khalil Ghorbal, Franjo Ivancic, Gogul Balakrishnan, Naoto Maeda, Aarti Gupta	Donut Domains: Efficient Non-convex Domains for Abstract Interpretation.	VMCAI	2012	DBLP DOI BibTeX RDF
1	Chao Wang, Sudipta Kundu, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta	Symbolic predictive analysis for concurrent programs.	Formal Asp. Comput.	2011	DBLP DOI BibTeX RDF
1	Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta	Predictive analysis for detecting serializability violations through Trace Segmentation.	MEMOCODE	2011	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Gogul Balakrishnan, Aarti Gupta, Sriram Sankaranarayanan, Naoto Maeda, Hiroki Tokuoka, Takashi Imoto, Yoshiaki Miyazaki	DC2: A framework for scalable, scope-bounded software verification.	ASE	2011	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Nipun Arora, Chao Wang, Aarti Gupta, Gogul Balakrishnan	BEST: A symbolic testing tool for predicting multi-threaded program failures.	ASE	2011	DBLP DOI BibTeX RDF
1	Prakash Prabhu, Naoto Maeda, Gogul Balakrishnan, Franjo Ivancic, Aarti Gupta	Interprocedural Exception Analysis for C++.	ECOOP	2011	DBLP DOI BibTeX RDF
1	Chao Wang, Mahmoud Said, Aarti Gupta	Coverage guided systematic concurrency testing.	ICSE	2011	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta	Numerical stability analysis of floating-point computations using software model checking.	MEMOCODE	2010	DBLP DOI BibTeX RDF
1	Chao Wang, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta	Trace-Based Symbolic Analysis for Atomicity Violations.	TACAS	2010	DBLP DOI BibTeX RDF
1	Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang	Scalable and precise program analysis at NEC.	FMCAD	2010	DBLP BibTeX RDF
1	Sicun Gao, Malay K. Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund M. Clarke	Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems.	FMCAD	2010	DBLP BibTeX RDF
1	William R. Harris, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta	Program analysis via satisfiability modulo path programs.	POPL	2010	DBLP DOI BibTeX RDF	program analysis, abstract interpretation, symbolic execution, path sensitivity, smt solvers, satisfiability solvers
1	Truong Nghiem, Sriram Sankaranarayanan, Georgios E. Fainekos, Franjo Ivancic, Aarti Gupta, George J. Pappas	Monte-carlo techniques for falsification of temporal properties of non-linear hybrid systems.	HSCC	2010	DBLP DOI BibTeX RDF	testing, robustness, hybrid systems, metric temporal logic
1	Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic	Model checking sequential software programs via mixed symbolic analysis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	composite symbolic formula, Model checking, binary decision diagram, reachability analysis, presburger arithmetic, image computation
1	Aarti Gupta, Sharad Malik	Preface.	Formal Methods in System Design	2009	DBLP DOI BibTeX RDF
1	Gogul Balakrishnan, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta	Refining the control structure of loops using static analysis.	EMSOFT	2009	DBLP DOI BibTeX RDF	loop refinement, synchronous sytems, model checking, static analysis, abstract interpretation, program verification, program understanding, path-sensitive analysis
1	Vineet Kahlon, Sriram Sankaranarayanan, Aarti Gupta	Semantic Reduction of Thread Interleavings in Concurrent Programs.	TACAS	2009	DBLP DOI BibTeX RDF
1	Chao Wang, Sudipta Kundu, Malay K. Ganai, Aarti Gupta	Symbolic Predictive Analysis for Concurrent Programs.	FM	2009	DBLP DOI BibTeX RDF
1	Georgios E. Fainekos, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta	Robustness of Model-Based Simulations.	IEEE Real-Time Systems Symposium	2009	DBLP DOI BibTeX RDF
1	Vineet Kahlon, Chao Wang, Aarti Gupta	Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique.	CAV	2009	DBLP DOI BibTeX RDF
1	Aarti Gupta	Model Checking Concurrent Programs.	VMCAI	2009	DBLP DOI BibTeX RDF
1	Chao Wang, Swarat Chaudhuri, Aarti Gupta, Yu Yang	Symbolic pruning of concurrent program executions.	ESEC/SIGSOFT FSE	2009	DBLP DOI BibTeX RDF	concurrency, sat, pruning, partial order reduction
1	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient SAT-based bounded model checking for software verification.	Theor. Comput. Sci.	2008	DBLP DOI BibTeX RDF
1	Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar	Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Aarti Gupta	Software Verification: Roles and Challenges for Automatic Decision Procedures.	IJCAR	2008	DBLP DOI BibTeX RDF
1	Chao Wang, Zijiang Yang, Vineet Kahlon, Aarti Gupta	Peephole Partial Order Reduction.	TACAS	2008	DBLP DOI BibTeX RDF
1	Sriram Sankaranarayanan, Swarat Chaudhuri, Franjo Ivancic, Aarti Gupta	Dynamic inference of likely data preconditions over predicates by tree learning.	ISSTA	2008	DBLP DOI BibTeX RDF	machine learning, verification, decision trees, sat, software specification
1	Chao Wang, Yu Yang, Aarti Gupta, Ganesh Gopalakrishnan	Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions.	ATVA	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Tunneling and slicing: towards scalable BMC.	DAC	2008	DBLP DOI BibTeX RDF	CFG, partitioning, slice, SMT, tunnel, EFSM, CSR, BMC
1	Malay K. Ganai, Aarti Gupta	Efficient Modeling of Concurrent Systems in BMC.	SPIN	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Completeness in SMT-based BMC for Software Programs.	DATE	2008	DBLP DOI BibTeX RDF
1	Aarti Gupta, Sharad Malik (eds.)	Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings	CAV	2008	DBLP BibTeX RDF
1	Gogul Balakrishnan, Sriram Sankaranarayanan, Franjo Ivancic, Ou Wei, Aarti Gupta	SLR: Path-Sensitive Analysis through Infeasible-Path Detection and Syntactic Language Refinement.	SAS	2008	DBLP DOI BibTeX RDF
1	Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta	Mining library specifications using inductive logic programming.	ICSE	2008	DBLP DOI BibTeX RDF	machine learning., verification, datalog, inductive logic programming, software specification
1	Fang Yu, Chao Wang, Aarti Gupta, Tevfik Bultan	Modular verification of web services using efficient symbolic encoding and summarization.	SIGSOFT FSE	2008	DBLP DOI BibTeX RDF	BPEL, summarization, modular verification
1	Malay K. Ganai, Muralidhar Talupur, Aarti Gupta	SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic.	JSAT	2007	DBLP BibTeX RDF
1	Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta	Disjunctive image computation for software verification.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Model checking, formal verification, binary decision diagram, reachability analysis, image computation
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Verification of Embedded Memory Systems using Efficient Memory Modeling	CoRR	2007	DBLP BibTeX RDF
1	Aarti Gupta, Tim Oates	Using Ontologies and the Web to Learn Lexical Semantics.	IJCAI	2007	DBLP BibTeX RDF
1	Chao Wang, Aarti Gupta, Franjo Ivancic	Induction in CEGAR for Detecting Counterexamples.	FMCAD	2007	DBLP DOI BibTeX RDF
1	Vineet Kahlon, Aarti Gupta	On the analysis of interacting pushdown systems.	POPL	2007	DBLP DOI BibTeX RDF	model checking, concurrency, dataflow analysis, LTL, mu-calculus, pushdown systems
1	Malay K. Ganai, Aarti Gupta	Efficient BMC for Multi-Clock Systems with Clocked Specifications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
1	Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi	Synthesizing "Verification Aware" Models: Why and How?	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Vineet Kahlon, Yu Yang, Sriram Sankaranarayanan, Aarti Gupta	Fast and Accurate Static Data-Race Detection for Concurrent Programs.	CAV	2007	DBLP DOI BibTeX RDF
1	Chao Wang, Zijiang Yang, Aarti Gupta, Franjo Ivancic	Using Counterexamples for Improving the Precision of Reachability Computation with Polyhedra.	CAV	2007	DBLP DOI BibTeX RDF
1	Aarti Gupta	From Hardware Verification to Software Verification: Re-use and Re-learn.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
1	Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta	Program Analysis Using Symbolic Ranges.	SAS	2007	DBLP DOI BibTeX RDF
1	Chao Wang, Hyondeuk Kim, Aarti Gupta	Hybrid CEGAR: combining variable hiding and predicate abstraction.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar	Efficient distributed SAT and SAT-based distributed Bounded Model Checking.	STTT	2006	DBLP DOI BibTeX RDF	Distributed-SAT, Parallel SAT, Model Checking, Formal Verification, SAT, BMC
1	Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic	Mixed symbolic representations for model checking software programs.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Muralidhar Talupur, Aarti Gupta	SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver.	TACAS	2006	DBLP DOI BibTeX RDF
1	Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta	Whodunit? Causal Analysis for Counterexamples.	ATVA	2006	DBLP DOI BibTeX RDF
1	Chao Wang, Aarti Gupta, Malay K. Ganai	Predicate learning and selective theory deduction for a difference logic solver.	DAC	2006	DBLP DOI BibTeX RDF	difference logic, SAT, decision procedure, SMT solver
1	Aarti Gupta, Malay K. Ganai, Chao Wang	SAT-Based Verification Methods and Applications in Hardware Verification.	SFM	2006	DBLP DOI BibTeX RDF
1	Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta	Disjunctive image computation for embedded software verification.	DATE	2006	DBLP DOI BibTeX RDF
1	Vineet Kahlon, Aarti Gupta, Nishant Sinha	Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions.	CAV	2006	DBLP DOI BibTeX RDF
1	Himanshu Jain, Franjo Ivancic, Aarti Gupta, Ilya Shlyakhter, Chao Wang	Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop.	CAV	2006	DBLP DOI BibTeX RDF
1	Vineet Kahlon, Aarti Gupta	An Automata-Theoretic Approach for Model Checking Threads for LTL Propert.	LICS	2006	DBLP DOI BibTeX RDF
1	Sriram Sankaranarayanan, Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta	Static Analysis in Disjunctive Numerical Domains.	SAS	2006	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Accelerating high-level bounded model checking.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Mukul R. Prasad, Armin Biere, Aarti Gupta	A survey of recent advances in SAT-based formal verification.	STTT	2005	DBLP DOI BibTeX RDF	Model checking, Verification, ATPG, SAT, QBF
1	Aarti Gupta, Ali Alphan Bayazit, Yogesh S. Mahajan	Verification Languages.	The Industrial Information Technology Handbook	2005	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems.	TACAS	2005	DBLP DOI BibTeX RDF
1	Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai	Localization and Register Sharing for Predicate Abstraction.	TACAS	2005	DBLP DOI BibTeX RDF
1	Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta	Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination.	LPAR	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Beyond safety: customized SAT-based model checking.	DAC	2005	DBLP DOI BibTeX RDF	circuit cofactoring, unbounded model checking, formal verification, SAT, liveness, bounded model checking, LTL
1	Aarti Gupta, Malay K. Ganai, Pranav Ashar	Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Verification of Embedded Memory Systems using Efficient Memory Modeling.	DATE	2005	DBLP DOI BibTeX RDF
1	Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip	Symmetry Reduction in SAT-Based Model Checking.	CAV	2005	DBLP DOI BibTeX RDF
1	Vineet Kahlon, Franjo Ivancic, Aarti Gupta	Reasoning About Threads Communicating via Locks.	CAV	2005	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar	F-Soft: Software Verification Platform.	CAV	2005	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai	Model Checking C Programs Using F-SOFT.	ICCD	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient Modeling of Embedded Memories in Bounded Model Checking.	CAV	2004	DBLP DOI BibTeX RDF
1	Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang	Efficient SAT-based Bounded Model Checking for Software Verification.	ISoLA (Preliminary proceedings)	2004	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar	Learning from BDDs in SAT-based bounded model checking.	DAC	2003	DBLP DOI BibTeX RDF	BDD learning, learning, SAT, BDDs, bounded model checking, boolean satisfiability, SAT solvers, property checking
1	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar	Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking.	CHARME	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar	Abstraction and BDDs Complement SAT-Based BMC in DiVer.	CAV	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar	Iterative Abstraction using SAT-based BMC with Proof Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta	Assertion-based verification turns the corner.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.	DAC	2002	DBLP DOI BibTeX RDF	boolean constraint propagation (BCP), bounded model checking (BMC), conjunctive normal form (CNF), boolean satisfiability (SAT)
1	Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi	Property-Specific Testbench Generation for Guided Simulation.	VLSI Design	2002	DBLP DOI BibTeX RDF	guided simulation, intelligent testbench generation, witness graph, property-specific testbench, approximate model checking, symbolic model checking, iterative refinement
1	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
1	Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar	Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation.	DAC	2001	DBLP DOI BibTeX RDF
1	Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar	Property-specific witness graph generation for guided simulation.	DATE	2001	DBLP DOI BibTeX RDF
1	Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik	Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.	ICCAD	2001	DBLP BibTeX RDF
1	Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta	SAT-Based Image Computation with Application in Reachability Analysis.	FMCAD	2000	DBLP DOI BibTeX RDF
1	Aarti Gupta, Pranav Ashar	Fast Error Diagnosis for Combinational Verification.	VLSI Design	2000	DBLP DOI BibTeX RDF	Satisfiability Checking, Formal Verification, Combinational Circuits, Binary Decision Diagrams, Logic Simulation, Error Diagnosis
1	Aarti Gupta, Pranav Ashar, Sharad Malik	Exploiting Retiming in a Guided Simulation Based Validation Methodology.	CHARME	1999	DBLP DOI BibTeX RDF
1	Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya	Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.	ICCD	1999	DBLP DOI BibTeX RDF
1	Aarti Gupta, Pranav Ashar	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.	VLSI Design	1998	DBLP DOI BibTeX RDF	ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
1	Aarti Gupta, Sharad Malik, Pranav Ashar	Toward Formalizing a Validation Methodology Using Simulation Coverage.	DAC	1997	DBLP DOI BibTeX RDF
1	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
1	Aarti Gupta, Allan L. Fisher	Tradeoffs in Canonical Sequential Function Representations.	ICCD	1994	DBLP BibTeX RDF
1	Aarti Gupta, Allan L. Fisher	Parametric Circuit Representation Using Inductive Boolean Functions.	CAV	1993	DBLP DOI BibTeX RDF
1	Aarti Gupta, Allan L. Fisher	Representation and symbolic manipulation of linearly inductive Boolean functions.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Aarti Gupta	Formal Hardware Verification Methods: A Survey.	Formal Methods in System Design	1992	DBLP DOI BibTeX RDF
1	Aarti Gupta, Allan L. Fisher	Flexible Parallel Polygon Rendering.	ICPP	1990	DBLP BibTeX RDF
1	Moon-Jung Chung, Edward J. Toy, Aarti Gupta	A Parallel Computer Based on Cube-Connected Cycles for Wafer-Scale.	FJCC	1986	DBLP BibTeX RDF

Publications of "Aarti Gupta" ( http://dblp.L3S.de/Authors/Aarti_Gupta )