Search results for "Abdel Ejnioui"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Abdel Ejnioui	Runtime Adaptation in Reconfigurable System-on-Chips.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, Paul Bao	A Parallel Array to Accelerate GFA Modeling in Video Coding.	ERSA	2008	DBLP BibTeX RDF
1	Abdel Ejnioui, Paul Bao	A parallel architecture for GFA modeling in video coding.	CIT	2008	DBLP DOI BibTeX RDF
1	Ronald F. DeMara, Yili Tseng, Abdel Ejnioui	Tiered Algorithm for Distributed Process Quiescence and Termination Detection.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Parallel Processing, Synchronization, Distributed Programming, Multitasking, Distributed Architectures
1	Abdel Ejnioui	FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Abdel Ejnioui	Prototyping of a Two-Phase Micropipeline on FPGAs.	ERSA	2007	DBLP BibTeX RDF
1	Abdel Ejnioui, Paul Bao	Hardware Acceleration of the Generalized Finite Automata Algorithm.	CDES	2007	DBLP BibTeX RDF
1	Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui	Synthesis of Pipelined SRSL Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler	Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study.	ERSA	2006	DBLP BibTeX RDF
1	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
1	Abdelhalim Alsharqawi, Abdel Ejnioui	Clockless Pipelining for Coarse Grain Datapaths.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Abdelhalim Alsharqawi, Abdel Ejnioui	Synthesis of Self-Resetting Stage Logic Pipelines.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, Ronald F. DeMara	Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices.	ERSA	2005	DBLP BibTeX RDF
1	Abdel Ejnioui, Abdelkader Rhiati	A Reconfigurable Memory Management Core for Java Applications.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui	Control and Data Flow Graph Extraction for High-Level Synthesis. (PDF / PS)	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
1	Abdel Ejnioui, N. Ranganathan	Routing on field-programmable switch matrices.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, N. Ranganathan	Multiterminal net routing for partial crossbar-based multi-FPGA systems.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	W. Kuang, J. S. Yuan, Abdel Ejnioui	Supply Voltage Scalable System Design Using Self-Timed Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	K. Sitaraman, N. Ranganathan, Abdel Ejnioui	A VLSI Architecture for Object Recognition Using Tree Matching.	ASAP	2002	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, N. Ranganathan	A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, N. Ranganathan	Design Partitioning on Single-Chip Emulation Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	FPGA partitioning, integer programming, FPGA architecture, schedule optimization
1	Abdel Ejnioui, N. Ranganathan	Routing on Switch Matrix Multi-FPGA Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	switch routing, Field programmable arrays, Multi-FPGA systems, Global routing, FPGA architecture, Interconnection structure
1	Vamsi Krishna, N. Ranganathan, Abdel Ejnioui	A tree-matching chip.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Abdel Ejnioui, N. Ranganathan	Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.	FPGA	1999	DBLP DOI BibTeX RDF	layout synthesis, integer programming, FPGA architecture, interconnect optimization, branch-and-price, FPGA routing
1	Vamsi Krishna, Abdel Ejnioui, N. Ranganathan	A tree matching chip.	VLSI Design	1996	DBLP DOI BibTeX RDF	tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture
1	Abdel Ejnioui, N. Ranganathan	Systolic algorithms for tree pattern matching. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	pattern tree, subject tree, PRAM model of computation, linear systolic array model, parallel algorithms, parallel algorithms, pattern matching, systolic arrays, SIMD machine, systolic algorithms, tree pattern matching

Publications of "Abdel Ejnioui" ( http://dblp.L3S.de/Authors/Abdel_Ejnioui )