Search results for "Abderrahim Doumar"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Farid Lahrach, Abderrahim Doumar, Eric Châtelet	Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems.	DSD	2011	DBLP DOI BibTeX RDF
1	Farid Lahrach, Abderrahim Doumar, Eric Châtelet	Fault tolerance of SRAM-based FPGA via configuration frames.	DDECS	2011	DBLP DOI BibTeX RDF
1	Farid Lahrach, Abderrahim Doumar, Eric Châtelet, Abderrazek Abdaoui	Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet	A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks.	DDECS	2010	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Kentaroh Katoh, Hideo Ito	Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.	DFT	2007	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Abderrahim Doumar, Hideo Ito	Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
1	Abderrahim Doumar, Hideo Ito	Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	An Automatic Testing and Diagnosis for FPGAs.	PRDC	1999	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Testing the Logic Cells and Interconnect Resources for FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito	Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF

Publications of "Abderrahim Doumar" ( http://dblp.L3S.de/Authors/Abderrahim_Doumar )