Search results for "Abhijit Jas"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	instruction-level error, microprocessor controller, Fault simulation, concurrent error detection
1	Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris	Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	scheduler, microprocessor, invariance, Concurrent error detection
1	Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	AVF Analysis Acceleration via Hierarchical Fault Pruning.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou	Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche	Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	microprocessor, on-line testing, control logic
1	Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas	FPGA-based hardware acceleration for Boolean satisfiability.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), boolean constant propagation (BCP), conflict induced clauses, non-chronological backtrack, FPGA
1	Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti	RT-Level Deviation-Based Grading of Functional Test Sequences.	VTS	2009	DBLP DOI BibTeX RDF
1	Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.	VTS	2009	DBLP DOI BibTeX RDF
1	Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Impact analysis of performance faults in modern microprocessors.	ICCD	2009	DBLP DOI BibTeX RDF
1	Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty	A Methodology for Handling Complex Functional Constraints for Large Industrial Designs.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Untestability analysis, Pseudo-functional tests, Functional constraints
1	Avijit Dutta, Abhijit Jas	Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.	ISQED	2008	DBLP DOI BibTeX RDF	EDAC, adhoc code, customizable codes, ECC
1	Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris	On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors.	ITC	2008	DBLP DOI BibTeX RDF
1	Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.	European Test Symposium	2008	DBLP DOI BibTeX RDF	microprocessor, error detecting codes, on-line testing, control logic
1	Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou	Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche	A low-cost concurrent error detection technique for processor control logic.	DATE	2008	DBLP DOI BibTeX RDF
1	Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti	Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.	DFT	2008	DBLP DOI BibTeX RDF
1	Abhijit Jas, Srinivas Patil	Analysis of Specified Bit Handling Capability of Combinational Expander Networks.	DFT	2007	DBLP DOI BibTeX RDF
1	Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty	An Approach to Minimizing Functional Constraints.	DFT	2006	DBLP DOI BibTeX RDF
1	C. V. Krishna, Abhijit Jas, Nur A. Touba	Achieving high encoding efficiency with partial dynamic LFSR reseeding.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	linear finite shift register, compression, Built-in self-test, reseeding
1	Abhijit Jas, C. V. Krishna, Nur A. Touba	Weighted pseudorandom hybrid BIST.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Abhijit Jas, Bahram Pouya, Nur A. Touba	Test data compression technique for embedded cores using virtual scan chains.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba	An efficient test vector compression scheme using selective Huffman coding.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Abhijit Jas, Nur A. Touba	Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	test data compression, system-on-chip testing, deterministic testing
1	C. V. Krishna, Abhijit Jas, Nur A. Touba	Test vector encoding using partial LFSR reseeding.	ITC	2001	DBLP DOI BibTeX RDF
1	Abhijit Jas, C. V. Krishna, Nur A. Touba	Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme.	VTS	2001	DBLP DOI BibTeX RDF
1	Abhijit Jas, Bahram Pouya, Nur A. Touba	Virtual Scan Chains: A Means for Reducing Scan Length in Cores.	VTS	2000	DBLP DOI BibTeX RDF	Compression/Decompression, Virtual Scan, Built-In Self-Test, Mapping, Design-for-Testability, LFSR, System Integrator, Integrated Circuits, Integrated Circuits, Scan Chains, Embedded Cores, Digital Testing, Reseeding
1	Abhijit Jas, Kartik Mohanram, Nur A. Touba	An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
1	Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba	Scan Vector Compression/Decompression Using Statistical Coding.	VTS	1999	DBLP DOI BibTeX RDF
1	W. Quddus, Abhijit Jas, Nur A. Touba	Configuration self-test in FPGA-based reconfigurable systems.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Abhijit Jas, Nur A. Touba	Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip.	ICCD	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
1	Abhijit Jas, Nur A. Touba	Test vector decompression via cyclical scan chains and its application to testing core-based designs.	ITC	1998	DBLP DOI BibTeX RDF

Publications of "Abhijit Jas" ( http://dblp.L3S.de/Authors/Abhijit_Jas )