Search results for "Adit D. Singh"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh	Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Xi Qian, Adit D. Singh, Abhijit Chatterjee	Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh	SSTKR: Secure and Testable Scan Design through Test Key Randomization.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Kautalya Mishra, Ahmed Faraz, Adit D. Singh	Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh	Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Xi Qian, Adit D. Singh	Distinguishing Resistive Small Delay Defects from Random Parameter Variations.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh	Modified Scan Flip-Flop for Low Power Testing.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh	Modified T-Flip-Flop based scan cell for RAS.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Adit D. Singh, Chao Han, Xi Qian	An output compression scheme for handling X-states from over-clocked delay tests.	VTS	2010	DBLP DOI BibTeX RDF
1	Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh	On Minimization of Test Application Time for RAS.	VLSI Design	2010	DBLP DOI BibTeX RDF	Random Access Scan (RAS), DFT, Scan Design
1	A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh	Test application time minimization for RAS using basis optimization of column decoder.	ISCAS	2010	DBLP DOI BibTeX RDF
1	K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh	Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal	Output Hazard-Free Transition Delay Fault Test Generation.	VTS	2009	DBLP DOI BibTeX RDF
1	Adit D. Singh	A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.	DFT	2009	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Chris Papachristou	Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Adit D. Singh	Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects.	ITC	2008	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee	Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Adit D. Singh	Scan Delay Testing of Nanometer SoCs.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Gefu Xu, Adit D. Singh	Scan cell design for launch-on-shift delay tests with slow scan enable.	IET Computers & Digital Techniques	2007	DBLP BibTeX RDF
1	Gefu Xu, Adit D. Singh	Achieving high transition delay fault coverage with partial DTSFF scan chains.	ITC	2007	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril	Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Gefu Xu, Adit D. Singh	Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Haihua Yan, Adit D. Singh	A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI).	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee	Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	IC reliability, reliability simulation, design for reliability, interconnect, electromigration, defect modeling
1	Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh	New JETTA Editors, 2006.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh	Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	fault tolerance, reliability, testing
1	Gefu Xu, Adit D. Singh	Low Cost Launch-on-Shift Delay Test with Slow Scan Enable.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Adit D. Singh, Gefu Xu	Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.	VTS	2006	DBLP DOI BibTeX RDF	Hazard-Free, Test, Delay, Transition
1	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak	Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Pseudo Dual Supply Voltage Domino Logic Design.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Haihua Yan, Gefu Xu, Adit D. Singh	Low Voltage Test in Place of Fast Clock in DDSI Delay Test.	ISQED	2005	DBLP DOI BibTeX RDF	delay test, defect, ATE, low voltage test
1	Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh	A random access scans architecture to reduce hardware overhead.	ITC	2005	DBLP DOI BibTeX RDF
1	Adit D. Singh	A self-timed structural test methodology for timing anomalies due to defects and process variations.	ITC	2005	DBLP DOI BibTeX RDF
1	Adit D. Singh	T2: Statistical Methods for VLSI Test and Burn-in Optimization.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Haihua Yan, Adit D. Singh, Gefu Xu	Delay Defect Characterization Using Low Voltage Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Low-power domino circuits using NMOS pull-up on off-critical paths.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.	VTS	2005	DBLP DOI BibTeX RDF
1	Haihua Yan, Adit D. Singh	A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.	ICCD	2005	DBLP DOI BibTeX RDF
1	Haihua Yan, Adit D. Singh	Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study.	ITC	2004	DBLP DOI BibTeX RDF
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
1	Haihua Yan, Adit D. Singh	Reduce Yield Loss in Delay Defect Detection in Slack Interval.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Sizing CMOS Circuits for Increased Transient Error Tolerance.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Extending integrated-circuit yield-models to estimate early-life reliability.	IEEE Transactions on Reliability	2003	DBLP DOI BibTeX RDF
1	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
1	Adit D. Singh	Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". (PDF / PS)	ISQED	2003	DBLP DOI BibTeX RDF
1	Adit D. Singh	Should Nanometer Circuits be Periodically Tested in the Field?	ITC	2003	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Adit D. Singh	Relating Yield Models to Burn-In Fall-Out in Time.	ITC	2003	DBLP DOI BibTeX RDF
1	Haihua Yan, Adit D. Singh	Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die.	ITC	2003	DBLP DOI BibTeX RDF
1	Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa	IC Reliability Simulator ARET and Its Application in Design-for-Reliability.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh	Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.	ITC	2002	DBLP DOI BibTeX RDF
1	Michael Gössel, Egor S. Sogomonyan, Adit D. Singh	Scan-Path with Directly Duplicated and Inverted Duplicated Registers.	VTS	2002	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy	Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction.	VTS	2002	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Estimating burn-in fall-out for redundant memory.	ITC	2001	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model.	VTS	2001	DBLP DOI BibTeX RDF
1	Egor S. Sogomonyan, A. A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh	Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.	VTS	2001	DBLP DOI BibTeX RDF
1	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
1	Egor S. Sogomonyan, Adit D. Singh, Michael Gössel	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	design-for-testability, BIST, scan design
1	David R. Lakin II, Adit D. Singh	Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study.	ITC	1999	DBLP DOI BibTeX RDF
1	Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring	Testability evaluation of sequential designs incorporating the multi-mode scannable memory element.	ITC	1999	DBLP DOI BibTeX RDF
1	Egor S. Sogomonyan, Adit D. Singh, Michael Gössel	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Adit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh	Binning for IC Quality: Experimental Studies on the SEMATECH Data. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF
1	Walter W. Weber, Adit D. Singh	Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	open faults, BIST, fault coverage, built in current sensor, BICS, I DDQ
1	Adit D. Singh, Phil Nigh, C. Mani Krishna	Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study.	ITC	1997	DBLP DOI BibTeX RDF
1	Christopher G. Knight, Adit D. Singh, Victor P. Nelson	An IDDQ Sensor for Concurrent Timing Error Detection. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF
1	Adit D. Singh, C. Mani Krishna	On the Effect of Defect Clustering on Test Transparency and IC Test Optimization.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	IC test optimization, defect clustering, wafer-based testing, adaptive testing
1	Jae Young Lee, Hee Yong Youn, Adit D. Singh	Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Adaptive voting, centralized testing, distributed self-diagnosis, identifiability, multiprocessor architectures
1	Adit D. Singh, Haroon Rasheed, Walter W. Weber	IDDQ Testing of CMOS Opens: An Experimental Study.	ITC	1995	DBLP DOI BibTeX RDF
1	Walter W. Weber, Adit D. Singh	An experimental evaluation of the differential BICS for I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	differential BICS, CMOS test chips, inter-layer shorts, intra-layer shorts, fault diagnosis, integrated circuit testing, fault coverage, CMOS integrated circuits, opens, built-in current sensor, IC testing, I/sub DDQ/ testing, electric current measurement, electric sensing devices
1	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
1	Adit D. Singh, C. Mani Krishna	On optimizing VLSI testing for product quality using die-yield prediction.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Jae Young Lee, Hee Yong Youn, Adit D. Singh	Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis.	FTCS	1993	DBLP DOI BibTeX RDF
1	Adit D. Singh, C. Mani Krishna	Chip Test Optimization Using Defect Clustering Information.	FTCS	1992	DBLP DOI BibTeX RDF
1	Adit D. Singh, Hee Yong Youn	A Modular Fault-Tolerant Binary Tree Architecture with Short Links.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	binary tree architecture, operational faults, fabrication defects, board level multichip designs, SOFT approach, fault-tolerant, VLSI, fault tolerant computing, computer architecture
1	Adit D. Singh, C. Mani Krishna	On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction.	ITC	1991	DBLP DOI BibTeX RDF
1	Adit D. Singh, Singaravel Murugesan	Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue.	IEEE Computer	1990	DBLP BibTeX RDF
1	Israel Koren, Adit D. Singh	Fault Tolerance in VLSI Circuits.	IEEE Computer	1990	DBLP DOI BibTeX RDF
1	Hee Yong Youn, Adit D. Singh	On Implementing Large Binary Tree Architectures in VLSI and WSI.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	large binary tree architectures, maximum edge length, H-tree layouts, VLSI, VLSI, layout, trees (mathematics), circuit layout CAD, processing elements, propagation delay, fault-tolerant designs, WSI, two-dimensional array
1	Hee Yong Youn, Adit D. Singh	A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI.	ICPP	1989	DBLP BibTeX RDF
1	C. Mani Krishna, Adit D. Singh	Modelling correlated transient failures in fault-tolerant systems.	FTCS	1989	DBLP DOI BibTeX RDF
1	Adit D. Singh	Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	area efficient fault tolerance scheme, large area VLSI processor arrays, interstitial sites, operational spares, area efficient layouts, chip area utilization, interstitial redundancy, PE survival probabilities, VLSI, fault tolerant computing, reconfiguration, redundancy, polynomial time algorithm, cellular arrays, switching network, performance degradation, wafer scale integration, circuit layout
1	Hee Yong Youn, Adit D. Singh	A Highly Efficient Design for Reconfiguring the Processor Array in VLSI.	ICPP	1988	DBLP BibTeX RDF
1	Hee Yong Youn, Adit D. Singh	Near Optimal Embedding of Binary Tree Architecture in VLSI.	ICDCS	1988	DBLP BibTeX RDF
1	Hee Yong Youn, Adit D. Singh	On Area Efficient and Fault Tolerant Tree Embedding In VLSI.	ICPP	1987	DBLP BibTeX RDF

Publications of "Adit D. Singh" ( http://dblp.L3S.de/Authors/Adit_D._Singh )