Search results for "Aditya Bansal"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Amith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal	DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM.	ISQED	2012	DBLP DOI BibTeX RDF
1	Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang	Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability.	Microelectronics Reliability	2009	DBLP DOI BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das	Yield estimation of SRAM circuits using "Virtual SRAM Fab".	ICCAD	2009	DBLP BibTeX RDF
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang	Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.	ICCD	2008	DBLP DOI BibTeX RDF
1	Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy	Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy	High Performance and Low Power Electronics on Flexible Substrate.	DAC	2007	DBLP DOI BibTeX RDF
1	Aditya Bansal, Bipul Chandra Paul, Kaushik Roy	An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy	A high density, carbon nanotube capacitor for decoupling applications.	DAC	2006	DBLP DOI BibTeX RDF	interconnect, carbon nanotube, three-dimensional, capacitor
1	Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy	Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-Gate SOI Devices for Low-Power and High-Performance Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.	DATE	2006	DBLP DOI BibTeX RDF
1	Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy	Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Aditya Bansal, Kaushik Roy	Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-gate SOI devices for low-power and high-performance applications.	ICCAD	2005	DBLP BibTeX RDF
1	Hari Ananthan, Aditya Bansal, Kaushik Roy	FinFET SRAM - Device and Circuit Design Considerations.	ISQED	2004	DBLP DOI BibTeX RDF

Publications of "Aditya Bansal" ( http://dblp.L3S.de/Authors/Aditya_Bansal )