Search results for "Adrián Cristal"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	Profiling and Optimizing Transactional Memory Applications.	International Journal of Parallel Programming	2012	DBLP DOI BibTeX RDF
1	J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Hardware transactional memory with software-defined conflicts.	TACO	2012	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache.	Integration	2012	DBLP DOI BibTeX RDF
1	Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero	TagTM - accelerating STMs with hardware tags for fast meta-data access.	DATE	2012	DBLP BibTeX RDF
1	Enrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman S. Unsal, Adrián Cristal, Mateo Valero	Hybrid Transactional Memory with Pessimistic Concurrency Control.	International Journal of Parallel Programming	2011	DBLP DOI BibTeX RDF
1	Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).	SIGMETRICS Performance Evaluation Review	2011	DBLP DOI BibTeX RDF
1	Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.	PACT	2011	DBLP DOI BibTeX RDF
1	Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero	Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.	PACT	2011	DBLP DOI BibTeX RDF
1	Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal	DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.	PACT	2011	DBLP DOI BibTeX RDF
1	Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.	PACT	2011	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache for optimistic concurrency.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero	TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.	FCCM	2011	DBLP DOI BibTeX RDF
1	Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero	From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.	ARC	2011	DBLP DOI BibTeX RDF
1	Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	RMS-TM: a comprehensive benchmark suite for transactional memory systems.	ICPE	2011	DBLP DOI BibTeX RDF
1	Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Mateo Valero	FIMSIM: A fault injection infrastructure for microarchitectural simulators.	ICCD	2011	DBLP DOI BibTeX RDF
1	Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel	The Velox Transactional Memory Stack.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero	Discovering and understanding performance bottlenecks in transactional applications.	PACT	2010	DBLP DOI BibTeX RDF
1	Tim Harris, Sasa Tomic, Adrián Cristal, Osman S. Unsal	Dynamic filtering: multi-purpose architecture support for language runtime systems.	ASPLOS	2010	DBLP DOI BibTeX RDF	garbage collection, transactional memory, runtime systems
1	Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero	Architectural Support for Fair Reader-Writer Locking.	MICRO	2010	DBLP DOI BibTeX RDF
1	Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrián Cristal, Mateo Valero	Debugging programs that use atomic blocks and transactional memory.	PPOPP	2010	DBLP DOI BibTeX RDF	debugging, transactional memory
1	Nehir Sönmez, Tim Harris, Adrián Cristal, Osman S. Unsal, Mateo Valero	Taking the heat off transactions: Dynamic selection of pessimistic concurrency control.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero	Clock gate on abort: Towards energy-efficient hardware Transactional Memory.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero	EazyHTM: eager-lazy hardware transactional memory.	MICRO	2009	DBLP DOI BibTeX RDF	EazyHTM, transactional memory
1	Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero	Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory.	HPCC	2009	DBLP DOI BibTeX RDF
1	Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero	QuakeTM: parallelizing a complex sequential application using transactional memory.	ICS	2009	DBLP DOI BibTeX RDF	game server, transactional memory
1	Ferad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero	Atomic quake: using transactional memory in an interactive multiplayer game server.	PPOPP	2009	DBLP DOI BibTeX RDF	benchmark, transactional memory, workload, quake
1	Chinmay Eishan Kulkarni, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero	Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions.	PPOPP	2009	DBLP DOI BibTeX RDF	parallel programming, concurrency, transactional memory, deadlocks, deadlock-detection
1	Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero	Nebelung: Execution Environment for Transactional OpenMP.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Compiler, OpenMP, Software Transactional Memory, Runtime system
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero	A Two-Level Load/Store Queue Based on Execution Locality.	ISCA	2008	DBLP DOI BibTeX RDF
1	Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero	A distributed processor state management architecture for large-window processors.	MICRO	2008	DBLP DOI BibTeX RDF
1	Cristian Perfumo, Nehir Sönmez, Srdjan Stipic, Osman S. Unsal, Adrián Cristal, Tim Harris, Mateo Valero	The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	haskell, transactional memory, instrumentation
1	Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero	Transactional Memory: An Overview.	IEEE Micro	2007	DBLP DOI BibTeX RDF	parallel programming, multithreading, transactional memory, memory architecture
1	Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero	Hardware Transactional Memory with Operating System Support, HTMOS.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
1	Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Transactional Memory and OpenMP.	IWOMP	2007	DBLP DOI BibTeX RDF	STM Library, Compiler, OpenMP, Software Transaction Memory
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A Flexible Heterogeneous Multi-Core Architecture.	PACT	2007	DBLP DOI BibTeX RDF
1	Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero	Implicit Transactional Memory in Kilo-Instruction Multiprocessors.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A decoupled KILO-instruction processor.	HPCA	2006	DBLP DOI BibTeX RDF
1	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
1	Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum	An asymmetric clustered processor based on value content.	ICS	2005	DBLP DOI BibTeX RDF	content aware architectures, cluster architectures
1	Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez	Chained In-Order/Out-of-Order DoubleCore Architecture.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero	Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor.	ISHPC	2005	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero	Decoupled State-Execute Architecture.	ISHPC	2005	DBLP DOI BibTeX RDF
1	Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa	A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.	ICCD	2005	DBLP DOI BibTeX RDF	Instruction Wakeup, Low Power, CAM, Issue Queue, Out-of-Order Processors
1	Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez	Toward kilo-instruction processors.	TACO	2004	DBLP DOI BibTeX RDF	multicheckpointing, instruction-level parallelism, Memory wall, kilo-instruction processors
1	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero	A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF
1	Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega	Future ILP processors.	IJHPCN	2004	DBLP DOI BibTeX RDF
1	Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa	A partitioned instruction queue to reduce instruction wakeup energy.	IJHPCN	2004	DBLP DOI BibTeX RDF
1	Adrián Cristal, Oliverio J. Santana, Mateo Valero	Maintaining Thousands of In-flight Instructions.	Euro-Par	2004	DBLP DOI BibTeX RDF
1	Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero	A Content Aware Integer Register File Organization.	ISCA	2004	DBLP DOI BibTeX RDF
1	Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero	A first glance at Kilo-instruction based multiprocessors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors
1	Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero	An Optimized Front-End Physical Register File with Banking and Writeback Filtering.	PACS	2004	DBLP DOI BibTeX RDF
1	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero	Out-of-Order Commit Processors.	HPCA	2004	DBLP DOI BibTeX RDF
1	Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero	Evaluating kilo-instruction multiprocessors.	WMPI	2004	DBLP DOI BibTeX RDF	ROB, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, kilo-instruction processors
1	Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero	A Case for Resource-conscious Out-of-order Processors.	Computer Architecture Letters	2003	DBLP DOI BibTeX RDF	checkpointing, instruction-level parallelism, resource utilization, memory latency, Out-of-order processor
1	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero	Kilo-instruction Processors.	ISHPC	2003	DBLP DOI BibTeX RDF
1	Marco A. Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero	A Simple Low-Energy Instruction Wakeup Mechanism.	ISHPC	2003	DBLP DOI BibTeX RDF	Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window

Publications of "Adrián Cristal" ( http://dblp.L3S.de/Authors/Adrián_Cristal )