Search results for "Ahmed Amine Jerraya"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Walid Lafi, Didier Lattard, Ahmed Amine Jerraya	A 3D reconfigurable platform for 4G telecom applications.	DATE	2011	DBLP BibTeX RDF
1	Walid Lafi, Didier Lattard, Ahmed Amine Jerraya	An efficient hierarchical router for large 3D NoCs.	International Symposium on Rapid System Prototyping	2010	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya	Convergence of design and fabrication technologies, a key enabler for HW-SW integration.	ASAP	2010	DBLP DOI BibTeX RDF
1	Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres	Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem.	DATE	2010	DBLP BibTeX RDF
1	Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan	Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.	Integration	2009	DBLP DOI BibTeX RDF
1	Katalin Popovici, Ahmed Amine Jerraya	Flexible and abstract communication and interconnect modeling for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Rolf Ernst	Panel session - Multicore, will Startups drive innovation?	DATE	2009	DBLP BibTeX RDF
1	Ahmed Amine Jerraya, Gabriela Nicolescu	Embedded tutorial - Understanding multicore technologies.	DATE	2009	DBLP BibTeX RDF
1	Walid Lafi, Didier Lattard, Ahmed Amine Jerraya	High level modelling and performance evaluation of address mapping in NAND flash memory.	ICECS	2009	DBLP DOI BibTeX RDF
1	Lobna Kriaa, Aimen Bouchhima, Marius Gligor, Anne-Marie Fouillart, Frédéric Pétrot, Ahmed Amine Jerraya	Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	HW/SW interfaces, Programming models, heterogeneous MPSoC
1	Katalin Popovici, Xavier Guerin, Frédéric Rousseau, Pier Stanislao Paolucci, Ahmed Amine Jerraya	Platform-based software design flow for heterogeneous MPSoC.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	multimedia, programming environment, software design, SystemC, Simulink, transaction level modeling, Multiprocessor system-on chip
1	Wayne Wolf, Ahmed Amine Jerraya, Grant Martin	Multiprocessor System-on-Chip (MPSoC) Technology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya	Integrating Abstract NoC Models within MPSoC Design.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	Pieter J. Mosterman, Don Orofino, Janos Sztipanovits, Ahmed Amine Jerraya, Wido Kruijtzer, Víctor Reyes, Christos G. Cassandras, Grant Martin	Automatically Realising Embedded Systems from High-Level Functional Models.	DATE	2008	DBLP DOI BibTeX RDF
1	Benaoumeur Senouci, Aimen Bouchhima, Frédéric Rousseau, Frédéric Pétrot, Ahmed Amine Jerraya	Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach.	IEEE Distributed Systems Online	2007	DBLP DOI BibTeX RDF
1	Flávio Rech Wagner, Wander O. Cesário, Ahmed Amine Jerraya	Hardware/software IP integration using the ROSES design environment.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	IP integration, Systems-on-chip
1	Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Ricardo Reis, Xavier Guerin, Ahmed Amine Jerraya	Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.	Design Autom. for Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi	Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip.	Design Autom. for Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne Wolf	Roundtable: Envisioning the Future for Multiprocessor SoC.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	multiprocessor, SoC, multicore, MPSoC, CPU, chip
1	Katalin Popovici, Xavier Guerin, Frédéric Rousseau, Pier Stanislao Paolucci, Ahmed Amine Jerraya	Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya	Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
1	Xavier Guerin, Katalin Popovici, Wassim Youssef, Frédéric Rousseau, Ahmed Amine Jerraya	Flexible Application Software Generation for Heterogeneous Multi-Processor System-on-Chip.	COMPSAC	2007	DBLP DOI BibTeX RDF
1	Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya	Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.	DAC	2007	DBLP DOI BibTeX RDF
1	Katalin Popovici, Ahmed Amine Jerraya	Simulink based hardware-software codesign flow for heterogeneous MPSoC.	SCSC	2007	DBLP DOI BibTeX RDF	hardware-software gradual refinement, multimedia applications, abstraction levels
1	Patrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya	Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transaction accurate level, hardware/software interface modeling, multiprocessor SoC design, automatic generation tools, system-on-chip, SystemC, abstraction level, architecture exploration
1	Márcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya	Software Performance Estimation in MPSoC Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF	cycle-accurate simulation model, software performance estimation, MPSoC design, software-dominated embedded systems, integrated methodology, bus-functional model, multiprocessor platform, MPEG4 encoder, neural networks, performance analysis, design space exploration, design validation
1	Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi	Buffer Size Reduction through Control-Flow Decomposition.	RTCSA	2007	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya	HW/SW implementation from abstract architecture models.	DATE	2007	DBLP DOI BibTeX RDF
1	Nacer-Eddine Zergainoh, Ludovic Tambour, Pascal Urard, Ahmed Amine Jerraya	Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems.	EURASIP J. Adv. Sig. Proc.	2006	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Trevor N. Mudge	Guest editorial: Concurrent hardware and software design for multiprocessor SoC.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF
1	Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya	Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Lobna Kriaa, Aimen Bouchhima, Wassim Youssef, Frédéric Pétrot, Anne-Marie Fouillart, Ahmed Amine Jerraya	Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF	Simulation interfaces, Service-based model, Interface design automation, Systems-on-Chip
1	Benaoumeur Senouci, Aimen Bouchhima, Frédéric Rousseau, Frédéric Pétrot, Ahmed Amine Jerraya	Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach".	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot	Programming models and HW-SW interfaces abstraction for multi-processor SoC.	DAC	2006	DBLP DOI BibTeX RDF	HW/SW interfaces, programming models, heterogeneous MPSoC
1	Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya	Buffer memory optimization for video codec application modeled in Simulink.	DAC	2006	DBLP DOI BibTeX RDF	memory size reduction, video codec application, Simulink
1	Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya	Functional modeling techniques for efficient SW code generation of video codec applications.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya	High-level architecture exploration for MPEG4 encoder with custom parameters.	ASP-DAC	2006	DBLP DOI BibTeX RDF	multiprocessors SOC architecture, customization, video encoder, architecture exploration, MPEG4
1	Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya	Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping
1	Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya	Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip.	IJES	2005	DBLP DOI BibTeX RDF
1	Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya	ChronoSym: a new approach for fast and accurate SoC cosimulation.	IJES	2005	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Wayne Wolf	Hardware/Software Interface Codesign for Embedded Systems.	IEEE Computer	2005	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, Hannu Tenhunen, Wayne Wolf	Guest Editors' Introduction: Multiprocessor Systems-on-Chips.	IEEE Computer	2005	DBLP DOI BibTeX RDF	SoCs, microprocessors, multiprocessor systems, MPSoCs, chip design, VLSI technology
1	Nacer-Eddine Zergainoh, Ludovic Tambour, Henri Michel, Ahmed Amine Jerraya	Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation.	Technique et Science Informatiques	2005	DBLP BibTeX RDF
1	Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya	Conception des interfaces logiciel-matériel pour l'intégration des mémoires globales dans les systèmes monopuces.	Technique et Science Informatiques	2005	DBLP BibTeX RDF
1	Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya	Hardware/Software Interfaces Design for SoC.	The Industrial Information Technology Handbook	2005	DBLP BibTeX RDF
1	Arnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya	Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Romain Lemaire, Fabien Clermidy, Y. Durand, Didier Lattard, Ahmed Amine Jerraya	Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Aimen Bouchhima, Xi Chen, Frédéric Pétrot, Wander O. Cesário, Ahmed Amine Jerraya	A unified HW/SW interface model to remove discontinuities between HW and SW design.	EMSOFT	2005	DBLP DOI BibTeX RDF	hardware dependent software, embedded systems, hardware/software interfaces
1	Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya	Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya	Scheduler implementation in MP SoC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard	IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Adriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau, Wander O. Cesário, Ahmed Amine Jerraya	Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	interface design automation, service-based model, systems-on-chip, hardware/software interfaces
1	Wander O. Cesário, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Ahmed Amine Jerraya	Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits.	Journal of Systems and Software	2004	DBLP DOI BibTeX RDF
1	Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya	A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip.	Annales des Télécommunications	2004	DBLP DOI BibTeX RDF
1	Flávio Rech Wagner, Wander O. Cesário, Luigi Carro, Ahmed Amine Jerraya	Strategies for the integration of hardware and software IP components in embedded systems-on-chip.	Integration	2004	DBLP DOI BibTeX RDF
1	Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya	An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
1	Adriano Sarmento, Wander O. Cesário, Ahmed Amine Jerraya	Automatic Building of Executable Models from Abstract SoC Architectures Made of Heterogeneous Subsystems.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
1	Arnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya	Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya	Long Term Trends for Embedded System Design.	DSD	2004	DBLP DOI BibTeX RDF
1	Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.	DAC	2004	DBLP DOI BibTeX RDF	data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC
1	Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya	Debugging HW/SW interface for MPSoC: video encoder system design case study.	DAC	2004	DBLP DOI BibTeX RDF	hardware-dependant software, hardware-software interface, debug, multiprocessor system-on-chip
1	Ahmed Amine Jerraya	EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya	Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava	Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software.	DATE	2004	DBLP DOI BibTeX RDF
1	Mohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya	Unified Component Integration Flow for Multi-Processor SoC Design and Validation.	DATE	2004	DBLP DOI BibTeX RDF
1	Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya	Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform.	Design Autom. for Emb. Sys.	2003	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya	Hot Topics at HLDVT 02.	IEEE Design & Test of Computers	2003	DBLP BibTeX RDF
1	Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya	Embedded Application Prototyping on a Communication-Restricted Reconfigurable.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
1	Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya	An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
1	Sungjoo Yoo, Ahmed Amine Jerraya	Introduction to Hardware Abstraction Layers for SoC.	DATE	2003	DBLP DOI BibTeX RDF
1	Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya	Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer.	DATE	2003	DBLP DOI BibTeX RDF
1	F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya	Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC).	MTV	2003	DBLP DOI BibTeX RDF
1	Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya	Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	hardware/software codesign, Performance estimation, multiprocessor architectures, architecture exploration, system-level simulation
1	Gabriela Nicolescu, Kjetil Svarstad, Wander O. Cesário, Lovic Gauthier, Damien Lyonnard, Sungjoo Yoo, Philippe Coste, Ahmed Amine Jerraya	Desiderata pour la spécification et la conception des systèmes électroniques.	Technique et Science Informatiques	2002	DBLP BibTeX RDF
1	Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya	Exploration de l'espace des solutions architecturales dans le codesign.	Technique et Science Informatiques	2002	DBLP BibTeX RDF
1	Wander O. Cesário, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Lovic Gauthier, Mario Diaz-Nava	Multiprocessor SoC Platforms: A Component-Based Design Approach.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava	Component-based design approach for multicore SoCs.	DAC	2002	DBLP DOI BibTeX RDF	HW/SW interfaces abstraction, multicore System-on-Chip, component-based design
1	Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya	Automatic generation of embedded memory wrapper for multiprocessor SoC.	DAC	2002	DBLP DOI BibTeX RDF	dystem-on-chip, memory wrapper generation, embedded memory, memory access
1	Shuvra S. Bhattacharyya, Trevor N. Mudge, Wayne Wolf, Ahmed Amine Jerraya (eds.)	Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002	CASES	2002	DBLP BibTeX RDF
1	Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu	Validation in a Component-Based Design Flow for Multicore SoCs.	ISSS	2002	DBLP DOI BibTeX RDF	validation, SoC, abstraction levels, component-based design, cosimulation
1	Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli	Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design.	ISSS	2002	DBLP DOI BibTeX RDF	memory wrapper generation, system-on-chip, embedded memory, memory access
1	Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya	Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design.	VLSI Design	2002	DBLP DOI BibTeX RDF	heterogeneous systems design, MOEMS, cosimulation
1	Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya	Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design.	DATE	2002	DBLP DOI BibTeX RDF
1	Joseph Borel, G. Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen	MEDEA+ and ITRS Roadmaps.	DATE	2002	DBLP DOI BibTeX RDF
1	Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya	Automatic generation and targeting of application-specificoperating systems and embedded systems software.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya	Two Enduring Questions for Computer Design.	IEEE Design & Test of Computers	2001	DBLP BibTeX RDF
1	Wander O. Cesário, Gabriela Nicolescu, Lovic Gauthier, Damien Lyonnard, Ahmed Amine Jerraya	Colif: A Design Representation for Application-Specific Multiprocessor SOCs.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	Wayne Wolf, Ahmed Amine Jerraya	Application-Specific System-on-a-Chip Multiprocessors.	IEEE Design & Test of Computers	2001	DBLP BibTeX RDF
1	Wander O. Cesário, Gabriela Nicolescu, Lovic Gauthier, Damien Lyonnard, Ahmed Amine Jerraya	Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
1	Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya	Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip.	DAC	2001	DBLP DOI BibTeX RDF
1	Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya	Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory.	VLSI-SOC	2001	DBLP BibTeX RDF
1	Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya	Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Kjetil Svarstad, Nezih Ben-Fredj, Gabriela Nicolescu, Ahmed Amine Jerraya	A higher level system communication model for object-oriented specification and design of embedded systems.	ASP-DAC	2001	DBLP DOI BibTeX RDF	CORBA
1	Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld	Programming models for network processors (Panel).	ISSS	2001	DBLP BibTeX RDF
1	Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya	An optimal memory allocation for application-specific multiprocessor system-on-chip.	ISSS	2001	DBLP BibTeX RDF
1	Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya	An efficient architecture model for systematic design of application-specific multiprocessor SoC.	DATE	2001	DBLP DOI BibTeX RDF
1	Kjetil Svarstad, Gabriela Nicolescu, Ahmed Amine Jerraya	A model for describing communication between aggregate objects in the specification and design of embedded systems.	DATE	2001	DBLP DOI BibTeX RDF
1	Ahmed Amine Jerraya, G. Matheron	Electronic system design methodology: Europe's positioning.	DATE	2001	DBLP DOI BibTeX RDF

Publications of "Ahmed Amine Jerraya" ( http://dblp.L3S.de/Authors/Ahmed_Amine_Jerraya )