| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Wenfa Zhan, Aiman El-Maleh |
A new scheme of test data compression based on equal-run-length coding (ERLC).  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman El-Maleh, Saif al Zahir, Esam Khan |
Test data compression based on geometric shapes. |
Computers & Electrical Engineering |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh |
A scheme of test data compression based on coding of even bits marking and selective output inversion. |
Computers & Electrical Engineering |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenfa Zhan, Aiman El-Maleh |
A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC). |
CSCWD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan |
Defect-tolerant n2-transistor structure for reliable nanoelectronic designs. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani |
Reconfigurable broadcast scan compression using relaxation-based test vector decomposition. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Esa Alghonaim, Aiman El-Maleh, Mohamed Adnan Landolsi |
New Technique for Improving Performance of LDPC Codes in the Presence of Trapping Sets. |
EURASIP J. Wireless Comm. and Networking |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Esa Alghonaim, Aiman El-Maleh, Mohamed Adnan Landolsi |
Using input/output queues to increase LDPC decoder performance. |
AICCSA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh |
Test data compression for system-on-a-chip using extended frequency-directed run-length code. |
IET Computers & Digital Techniques |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh |
Efficient test compression technique based on block merging. |
IET Computers & Digital Techniques |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki |
Transistor-level based defect tolerance for reliable nanoelectronics. |
AICCSA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman El-Maleh, S. Saqib Khursheed |
Efficient test compaction for combinational circuits based on Fault detection count-directed clustering. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman El-Maleh |
An efficient test vector compression technique based on block merging. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji |
Evolutionary algorithms for VLSI multi-objective netlist partitioning. |
Eng. Appl. of AI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait |
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Sadiq M. Sait, F. Nawaz Khan |
Finite state machine state assignment for area and power minimization. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait |
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Khaled Al-Utaibi |
An efficient test relaxation technique for synchronous sequential circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Yahya E. Osais |
Test vector decomposition-based static compaction algorithms for combinational circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
Static compaction, class-based clustering, independent fault clustering, test vector decomposition, taxonomy, combinational circuits |
| 1 | Aiman H. El-Maleh, Khaled Al-Utaibi |
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji |
General iterative heuristics for VLSI multiobjective partitioning. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji |
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Khaled Al-Utaibi |
On efficient extraction of partially specified test sets for synchronous sequential circuits. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman El-Maleh, Ali Al-Suwaiyan |
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman El-Maleh, Esam Khan, Saif al Zahir |
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Yahya E. Osais |
A retiming-based test pattern generator design for built-in self test of data path architectures. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh |
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. |
ICCD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Mark Kassab, Janusz Rajski |
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
model checking, verification, guided search |
| 1 | Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly |
Behavior and testability preservation under the retiming transformation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski |
A complexity analysis of sequential ATPG. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Janusz Rajski |
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly |
Testability Implications of Performance-Driven Logic Synthesis. |
IEEE Design & Test of Computers |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly |
On Test Set Preservation of Retimed Circuits. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")