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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 47 occurrences of 32 keywords
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Found 84 publication records. Showing 84 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Rich Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo |
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.  |
DATE  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino |
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino |
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii |
Power-aware partitioning of data converters. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella |
An integrated thermal estimation framework for industrial embedded platforms. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
system-on-chip, power, estimation, thermal |
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses. |
J. Embedded Computing |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino |
Data-Driven Clock Gating for Digital Filters. |
PATMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Enabling concurrent clock and power gating in an industrial design flow. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
Placement-aware Clustering for Integrated Clock and Power Gating. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino |
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
| 1 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
A Scalable Algorithmic Framework for Row-Based Power-Gating. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Timing-driven row-based power gating. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
| 1 | Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
layout, leakage power, insertion, standard-cell, sleep transistor |
| 1 | Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino |
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic thermal clock skew compensation using tunable delay buffers. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
temperature aware design methodology, tunable delay buffers, clock skew, clock tree |
| 1 | Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii |
Enabling fine-grain leakage management by voltage anchor insertion. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino |
Thermal resilient bounded-skew clock tree optimization methodology. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Macii |
Low-power embedded systems. |
J. Embedded Computing |
2005 |
DBLP BibTeX RDF |
|
| 1 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii |
Low-overhead state-retaining elements for low-leakage MTCMOS design. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
MTCMOS design, state-retention, leakage power |
| 1 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
DBL, DWL, partitioning, embedded, memories, SRAM, application-specific |
| 1 | Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii |
Memory energy minimization by data compression: algorithms, architectures and implementation. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii |
Post-layout leakage power minimization based on distributed sleep transistor insertion. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
sub-threshold current, leakage power, sleep transistor |
| 1 | Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii |
Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Massimo Poncino |
Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. |
ACM Trans. Embedded Comput. Syst. |
2003 |
DBLP DOI BibTeX RDF |
nonvolatile, Embedded systems, integration, memories, system-on-a-chip, embedded memories, volatile |
| 1 | Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii, Massimo Poncino |
Discharge Current Steering for Battery Lifetime Optimization. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
Battery-operated electronics, low-power design, dynamic power management |
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Scheduling battery usage in mobile systems. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii |
Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurizio Bruno, Alberto Macii, Massimo Poncino |
A Statistic Power Model for Non-synthetic RTL Operators. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino |
Energy-efficient data scrambling on memory-processor interfaces. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
data scrambling, bus encoding, power attacks |
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro |
A novel architecture for power maskable arithmetic units. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
security, cryptography, low-power design |
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino |
Energy-aware design techniques for differential power analysis protection. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
low-power design, differential power analysis |
| 1 | Alberto Macii, Enrico Macii, Massimo Poncino |
Improving the Efficiency of Memory Partitioning by Address Clustering. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon |
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
Data compression algorithms, system-level energy optimization, VLIW embedded processors |
| 1 | Alberto Macii, Enrico Macii, Massimo Poncino |
Increasing the locality of memory access patterns by low-overhead hardware address relocation. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Minimizing memory access energy in embedded systems by selective instruction compression. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino |
Layout-driven memory synthesis for embedded systems-on-chip. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Macii, Luca Benini, Massimo Poncino |
Memory design techniques for low energy embedded systems. |
|
2002 |
RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii |
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Discharge current steering for battery lifetime optimization. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
battery lifetime optimization, energy consumption |
| 1 | Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino |
Enhanced clustered voltage scaling for low power. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii |
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Davide Bruni, Bruno Riccò, Alberto Macii, Enrico Macii |
An adaptive data compression scheme for memory traffic minimization in processor-based systems. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Stream synthesis for efficient power simulation based on spectral transforms. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Discrete-time battery models for system-level low-power design. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giuliano Castelli, Alberto Macii, Riccardo Scarsi |
Battery-Driven Dynamic Power Management. |
IEEE Design & Test of Computers |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Alberto Nannarelli |
Cached-code compression for energy minimization in embedded processors. |
ISLPED |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino |
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Extending lifetime of portable systems by battery scheduling. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Massimo Poncino, Riccardo Scarsi |
Architectures and synthesis algorithms for power-efficient businterfaces. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Glitch power minimization by selective gate freezing. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. |
IEEE Design & Test of Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Massimo Poncino |
A recursive algorithm for low-power memory partitioning. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino |
Supporting system-level power exploration for DSP applications. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Synthesis of application-specific memories for power optimization in embedded systems. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi |
Battery-Driven Dynamic Power Management of Portable Systems. |
ISSS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
A Discrete-Time Battery Model for High-Level Power Estimation. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Selective instruction compression for memory energy reduction in embedded systems. |
ISLPED |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi |
Regression-Based Macromodeling for Delay Estimation of Behavioral Components. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Glitch Power Minimization by Gate Freezing. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Stream synthesis for efficient power simulation based on spectral transforms. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino |
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
Low-Power Design, Microprocessors |
| 1 | Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi |
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
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