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Publications of "Alejandro Valero" ( http://dblp.L3S.de/Authors/Alejandro_Valero )

  Author page on DBLP  Author page in RDF  Community of Alejandro Valero in ASPL-2

Publication years (Num. hits)
2009 (1) 2011 (1) 2012 (1)
Publication types (Num. hits)
article(1) inproceedings(2)
Venues (Conferences, Journals, ...)
IEEE Trans. VLSI Syst.(1) MICRO(1) PACT(1)
Authors
Alejandro Valero(3) José Duato(3) Julio Sahuquillo(3) Pedro López(3) Salvador Petit(3) Vicente Lorente(2) Ramon Canal(1)
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Found 3 publication records. Showing 3 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. Search on Bibsonomy PACT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato An hybrid eDRAM/SRAM macrocell to implement first-level data caches. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF retention time, static and dynamic memory cells, leakage current
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