Search results for "Alex Ramírez"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero	On the simulation of large-scale architectures using multiple application abstraction levels.	TACO	2012	DBLP DOI BibTeX RDF
1	Santi González, Bàrbara Montserrat-Sentís, Friman Sánchez, Montserrat Puiggròs, Enrique Blanco, Alex Ramírez, David Torrents	ReLA, a local alignment search tool for the identification of distal and proximal gene regulatory regions and their conserved transcription factor binding sites.	Bioinformatics	2012	DBLP DOI BibTeX RDF
1	Nikola Vujic, Felipe Cabarcas, Marc González Tallada, Alex Ramírez, Xavier Martorell, Eduard Ayguadé	DMA++: On the Fly Data Realignment for On-Chip Memories.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Harm Munk, Eduard Ayguadé, Cédric Bastoul, Paul M. Carpenter, Zbigniew Chamski, Albert Cohen, Marco Cornero, Philippe Dumont, Marc Duranton, Mohammed Fellahi, Roger Ferrer, Razya Ladelsky, Menno Lindwer, Xavier Martorell, Cupertino Miranda, Dorit Nuzman, Andrea C. Ornstein, Antoniu Pop, Sebastian Pop, Louis-Noël Pouchet, Alex Ramírez, David Ródenas, Erven Rohou, Ira Rosen, Uzi Shvadron, Konrad Trifunovic, Ayal Zaks	ACOTES Project: Advanced Compiler Technologies for Embedded Streaming.	International Journal of Parallel Programming	2011	DBLP DOI BibTeX RDF
1	Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Scalable multicore architectures for long DNA sequence comparison.	Concurrency and Computation: Practice and Experience	2011	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero	A Highly Scalable Parallel Implementation of H.264.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	Dynamic Cache Partitioning Based on the MLP of Cache Misses.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Juan Gonzalez, Judit Gimenez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero	Simulating Whole Supercomputer Applications.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Augusto Vega, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Breaking the bandwidth wall in chip multiprocessors.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Alex Ramírez	Supercomputing: Past, present, and a possible future.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Carlos Villavieja, Yoav Etsion, Alex Ramírez, Nacho Navarro	FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores.	Euro-Par	2011	DBLP DOI BibTeX RDF
1	Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero	Trace-driven simulation of multithreaded applications.	ISPASS	2011	DBLP DOI BibTeX RDF
1	Catalin Bogdan Ciobanu, Xavier Martorell, Georgi Kuzmanov, Alex Ramírez, Georgi Gaydadjiev	Scalability Evaluation of a Polymorphic Register File: A CG Case Study.	ARCS	2011	DBLP DOI BibTeX RDF
1	Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal	DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.	PACT	2011	DBLP DOI BibTeX RDF
1	Sebastian Isaza, Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Georgi Gaydadjiev	Parametrizing multicore architectures for multiple sequence alignment.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Sebastian Isaza, Ernst Houtgast, Friman Sánchez, Alex Ramírez, Georgi Gaydadjiev	Scaling HMMER Performance on Multicore Architectures.	CISIS	2011	DBLP DOI BibTeX RDF
1	Alex Ramírez, Felipe Cabarcas, Ben H. H. Juurlink, Mauricio Alvarez, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Bogdan Ciobanu, Sebastian Isaza, Georgi Gaydadjiev	The SARC Architecture.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Veerle Desmet, Sylvain Girbal, Alex Ramírez, Olivier Temam, Augusto Vega	ArchExplorer for Automatic Design Space Exploration.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Richard Aló, Diane Baxter, Karl Barnes, Al Kuslikis, Geoffrey Fox, Alex Ramírez	Advancing Computational Science, Visualization and Homeland Security Research/ Education at Minority Serving Institutions National Model Promoted/ Implemented by MSI-CIEC (Minority Serving Institutions-CyberInfrastructure Empowerment Coalition).	Procedia CS	2010	DBLP DOI BibTeX RDF
1	Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez	Interleaving granularity on high bandwidth memory architecture for CMPs.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev, Alex Ramírez	A Polymorphic Register File for matrix operations.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Long DNA Sequence Comparison on Multicore Architectures.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Starsscheck: A Tool to Find Errors in Task-Based Parallel Programs.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Milan Pavlovic, Yoav Etsion, Alex Ramírez	Can Manycores Support the Memory Requirements of Scientific Applications?	ISCA Workshops	2010	DBLP DOI BibTeX RDF
1	Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Task Superscalar: An Out-of-Order Task Pipeline.	MICRO	2010	DBLP DOI BibTeX RDF
1	Alex Ramírez, Shaobo Ji, Rob Riordan, Frank Ulbrich, Michael J. Hine	Empowering Business Students - Using Web 2.0 Tools in the Classroom.	CSEDU	2010	DBLP BibTeX RDF
1	Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero	Scalability Analysis of Progressive Alignment on a Multicore.	CISIS	2010	DBLP DOI BibTeX RDF	clustalw, bioinformatics, multicore, multiple sequence alignment, cell
1	Nikola Vujic, Marc González, Felipe Cabarcas, Alex Ramírez, Xavier Martorell, Eduard Ayguadé	DMA++: on the fly data realignment for on-chip memories.	HPCA	2010	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Alejandro Rico, Alex Ramírez, Mateo Valero	Available task-level parallelism on the Cell BE.	Scientific Programming	2009	DBLP DOI BibTeX RDF
1	Pieter Bellens, Josep M. Pérez, Felipe Cabarcas, Alex Ramírez, Rosa M. Badia, Jesús Labarta	CellSs: Scheduling techniques to better exploit memory hierarchy.	Scientific Programming	2009	DBLP DOI BibTeX RDF
1	Mauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck	Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA.	RASI	2009	DBLP BibTeX RDF
1	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	DIA: A Complexity-Effective Decoding Architecture.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez	Parallel Scalability of Video Decoders.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero	FlexDCP: a QoS framework for CMP architectures.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors.	SAMOS	2009	DBLP DOI BibTeX RDF
1	M. Alvarez Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero	Scalability of Macroblock-level Parallelism for H.264 Decoding.	ICPADS	2009	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Mapping stream programs onto heterogeneous multiprocessor systems.	CASES	2009	DBLP DOI BibTeX RDF	partitioning, multicore, convexity, stream programming
1	Friman Sánchez, Alex Ramírez, Mateo Valero	Quantitative analysis of sequence alignment applications on multiprocessor architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	bioinformatics applications, parallel architectures, multiprocessor architectures, sequence comparison
1	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	Thread to Core Assignment in SMT On-Chip Multiprocessors.	SBAC-PAD	2009	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez	Parallel H.264 Decoding on an Embedded Multicore Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith	Multicore Resource Management.	IEEE Micro	2008	DBLP DOI BibTeX RDF
1	Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero	Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.	ICPP	2008	DBLP DOI BibTeX RDF
1	Alex Ramírez, Gianfranco Bilardi, Michael Gschwind (eds.)	Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008	Conf. Computing Frontiers	2008	DBLP BibTeX RDF
1	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez	Analysis of video filtering on the cell processor.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	Explaining Dynamic Cache Partitioning Speed Ups.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam	High-Performance Embedded Architecture and Compilation Roadmap.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	HiPEAC, single core architecture, programming models and tools, simulation and system modelling, real-time systems, compilation, interconnection networks, benchmarking, reconfigurable computing, run-time systems, multi-core architecture, roadmap
1	Oliverio J. Santana, Alex Ramírez, Mateo Valero	Enlarging Instruction Streams.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Superscalar processor design, branch prediction, code optimization, instruction fetch, access latency
1	Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero	On the Problem of Minimizing Workload Execution Time in SMT Processors.	ICSAMOS	2007	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	Online Prediction of Applications Cache Utility.	ICSAMOS	2007	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé	A Streaming Machine Description and Programming Model.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
1	Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero	Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	auto vectorizing compiler, unaligned memory operations, SIMD extensions, video codec applications, unaligned memory accesses, H.264/AVC media codec, memory architecture, data level parallelism
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	PACT	2007	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Predictable Performance in SMT Processors: Synergy between the OS and SMTs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	real time, operating systems, performance predictability, ILP, thread-level parallelism, simultaneous multithreading, Multithreaded processors
1	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	Branch predictor guided instruction decoding.	PACT	2006	DBLP DOI BibTeX RDF	complexity-effective, instruction decoding, branch predictor
1	Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero	Performance Analysis of Sequence Alignment Applications.	IISWC	2006	DBLP DOI BibTeX RDF
1	Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero	Better Branch Prediction Through Prophet/Critic Hybrids.	IEEE Micro	2005	DBLP DOI BibTeX RDF
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	Software Trace Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	compiler optimizations, branch prediction, Pipeline processors, trace cache, instruction fetch
1	Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero	On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications.	ISPASS	2005	DBLP DOI BibTeX RDF
1	Ayose Falcón, Alex Ramírez, Mateo Valero	Effective Instruction Prefetching via Fetch Prestaging.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero	A Complexity-Effective Simultaneous Multithreading Architecture.	ICPP	2005	DBLP DOI BibTeX RDF	Complexity-Effective, Heterogeneity-Awareness, Mapping Policies, Clustering, CMP, SMT
1	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Architectural support for real-time task scheduling in SMT processors.	CASES	2005	DBLP DOI BibTeX RDF	scheduling, real time, multithreading, performance predictability, ILP, thread-level parallelism, SMT
1	Nader Bagherzadeh, Mateo Valero, Alex Ramírez (eds.)	Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005	Conf. Computing Frontiers	2005	DBLP BibTeX RDF
1	Oliverio J. Santana, Alex Ramírez, Mateo Valero	Multiple Stream Prediction.	ISHPC	2005	DBLP DOI BibTeX RDF
1	Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	A low-complexity fetch architecture for high-performance superscalar processors.	TACO	2004	DBLP DOI BibTeX RDF	fetch architecture, instruction stream, high performance, Branch prediction, low complexity
1	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández	QoS for High-Performance SMT Processors in Embedded Systems.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero	A latency-conscious SMT branch prediction architecture.	IJHPCN	2004	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández	Optimising long-latency-load-aware fetch policies for SMT processors.	IJHPCN	2004	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Feasibility of QoS for SMT.	Euro-Par	2004	DBLP DOI BibTeX RDF
1	Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero	Prophet/Critic Hybrid Branch Prediction.	ISCA	2004	DBLP DOI BibTeX RDF
1	Oliverio J. Santana, Alex Ramírez, Mateo Valero	Reducing Fetch Architecture Complexity Using Procedure Inlining.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Implicit vs. Explicit Resource Allocation in SMT Processors.	DSD	2004	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández	DCache Warn: An I-Fetch Policy to Increase SMT Efficiency.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández	Dynamically Controlled Resource Allocation in SMT Processors.	MICRO	2004	DBLP DOI BibTeX RDF
1	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Predictable performance in SMT processors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	real time, operating systems, multithreading, performance predictability, ILP, thread-level parallelism, SMT
1	Ayose Falcón, Alex Ramírez, Mateo Valero	A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors.	HPCA	2004	DBLP DOI BibTeX RDF
1	Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero	Tolerating Branch Predictor Latency on SMT.	ISHPC	2003	DBLP DOI BibTeX RDF	branch predictor delay, decoupled fetch, predictorpipelining, SMT
1	Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero	Improving Memory Latency Aware Fetch Policies for SMT Processors.	ISHPC	2003	DBLP DOI BibTeX RDF	fetch policy, long latency loads, load miss predictors, multithreading, SMT
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas	Software Trace Cache for Commercial Applications.	International Journal of Parallel Programming	2002	DBLP DOI BibTeX RDF
1	Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero	A Comparative Study of Redundancy in Trace Caches (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
1	Alex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero	Fetching instruction streams.	MICRO	2002	DBLP DOI BibTeX RDF	Systems Application Architecture
1	Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero	A Comprehensive Analysis of Indirect Branch Prediction.	ISHPC	2002	DBLP BibTeX RDF	indirect branch, Multi-Stage Cascaded Predictor, branch prediction, microarchitecture, Branch Target Buffer
1	Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero	Studying New Ways for Improving Adaptive History Length Branch Predictors.	ISHPC	2002	DBLP BibTeX RDF	dynamic history length, warm-up, branch prediction, opportunity cost
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	Branch Prediction Using Profile Data.	Euro-Par	2001	DBLP DOI BibTeX RDF
1	Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero	Code layout optimizations for transaction processing workloads.	ISCA	2001	DBLP DOI BibTeX RDF
1	Carlos Navarro, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	On the Performance of Fetch Engines Running DSS Workloads.	Euro-Par	2000	DBLP DOI BibTeX RDF
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	The Effect of Code Reordering on Branch Prediction.	IEEE PACT	2000	DBLP DOI BibTeX RDF
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	Trace Cache Redundancy: Red & Blue Traces.	HPCA	2000	DBLP DOI BibTeX RDF	trace cache, instruction fetch, code reordering
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas	Optimization of Instruction Fetch for Decision Support Workloads. (PDF / PS)	ICPP	1999	DBLP DOI BibTeX RDF	High performance fetch, databases, profiling, compiler optimization, trace cache
1	Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero	Software trace cache.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF

Publications of "Alex Ramírez" ( http://dblp.L3S.de/Authors/Alex_Ramírez )