Search results for "Alexander Saldanha"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wilsin Gosti, Tiziano Villa, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	FSM Encoding for BDD Representations.	Applied Mathematics and Computer Science	2007	DBLP DOI BibTeX RDF
1	Eugene Goldberg, Alexander Saldanha	Timing Analysis with Implicitly Specified False Paths.	VLSI Design	2000	DBLP DOI BibTeX RDF	known false paths, implicit false path representation, timing analysis, breadth-first search
1	Alexander Saldanha	Functional timing optimization.	ICCAD	1999	DBLP BibTeX RDF
1	Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	A methodology for correct-by-construction latency insensitive design.	ICCAD	1999	DBLP BibTeX RDF
1	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial-scan delay fault testing of asynchronous circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha	An Exact Input Encoding Algorithm for BDDs Representing FSMs.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	input encoding, finite state machines, binary decision diagrams, multi-valued decision diagrams
1	Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Symbolic two-level minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton	Approximate timing analysis of combinational circuits under the XBD0 model.	ICCAD	1997	DBLP DOI BibTeX RDF	delay computation, timing analysis, False path
1	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
1	Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	Trace driven logic synthesis&mdashapplication to power minimization.	ICCAD	1997	DBLP DOI BibTeX RDF	Low Power, Logic Synthesis
1	Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha	Verification of Electronic Systems.	DAC	1996	DBLP DOI BibTeX RDF
1	Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Compact and complete test set generation for multiple stuck-faults.	ICCAD	1996	DBLP DOI BibTeX RDF	Multiple stuck faults, complete test set generation, irrepressible faults
1	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Delay fault coverage, test set size, and performance trade-offs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool.	DAC	1995	DBLP DOI BibTeX RDF
1	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Functional clock schedule optimization.	VLSI Design	1995	DBLP DOI BibTeX RDF	clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
1	Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha	Supervisory Control of Finite State Machines.	CAV	1995	DBLP DOI BibTeX RDF
1	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
1	Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Satisfaction of input and output encoding constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Circuit structure relations to redundancy and delay.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Performance Optimization Using Exact Sensitization.	DAC	1994	DBLP DOI BibTeX RDF
1	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Delay Fault Coverage and Performance Tradeoffs.	DAC	1993	DBLP DOI BibTeX RDF
1	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation.	DAC	1992	DBLP BibTeX RDF
1	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited.	DAC	1992	DBLP BibTeX RDF
1	Kurt Keutzer, Sharad Malik, Alexander Saldanha	Is redundancy necessary to reduce delay?	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	A Framework for Satisfying Input and Output Encoding Constraints.	DAC	1991	DBLP DOI BibTeX RDF
1	Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.	ICCAD	1991	DBLP BibTeX RDF
1	Kurt Keutzer, Sharad Malik, Alexander Saldanha	Is Redundancy Necessary to Reduce Delay.	DAC	1990	DBLP DOI BibTeX RDF
1	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng	Timing Optimization with Testability Considerations.	ICCAD	1990	DBLP BibTeX RDF
1	Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Multi-level Logic Simplification Using Don't Cares and Filters.	DAC	1989	DBLP DOI BibTeX RDF

Publications of "Alexander Saldanha" ( http://dblp.L3S.de/Authors/Alexander_Saldanha )