| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum |
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.  |
IEEE Trans. VLSI Syst.  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari |
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Cammarota, Arun Kejariwal, Paolo D'Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, Alexandru Nicolau |
Pruning hardware evaluation space via correlation-driven application similarity analysis. |
Conf. Computing Frontiers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi |
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum |
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
computer aided design, placement, dynamic reconfiguration, temperature, reconfigurable systems |
| 1 | Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos |
Exploitation of nested thread-level speculative parallelism on multi-core systems. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
performance, thread-level speculation |
| 1 | Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt |
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power |
| 1 | Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos |
On the efficacy of call graph-level thread-level speculation. |
WOSP/SIPEW |
2010 |
DBLP DOI BibTeX RDF |
performance, thread-level speculation |
| 1 | Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt |
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. |
HiPEAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayram Moorkanikara Nageswaran, Andrew Felch, Ashok Chandrasekhar, Nikil Dutt, Richard Granger, Alex Nicolau, Alexander V. Veidenbaum |
Brain Derived Vision Algorithm on High Performance Architectures. |
International Journal of Parallel Programming |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito |
On the exploitation of loop-level parallelism in embedded applications. |
ACM Trans. Embedded Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
multithreading, Multi-cores, vectorization, libraries, programming models, thread-level speculation, parallel loops, system-on-chip (Soc) |
| 1 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum |
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. |
Neural Networks |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy |
Performance Characterization of Itanium® 2-Based Montecito Processor. |
SPEC Benchmark Workshop |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum |
Power-aware load balancing of large scale MPI applications. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Kejariwal, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos |
Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. |
ICPP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gearold Johnson, Carsten Trinitis, Georgi Gaydadjiev, Alexander V. Veidenbaum (eds.) |
Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009 |
Conf. Computing Frontiers |
2009 |
DBLP BibTeX RDF |
|
| 1 | Alexandru Nicolau, Guangqiang Li, Alexander V. Veidenbaum, Arun Kejariwal |
Synchronization optimizations for efficient execution on multi-cores. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
compilers, synchronization, multithreading, code motion |
| 1 | Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos |
Cache-aware partitioning of multi-dimensional iteration spaces. |
SYSTOR |
2009 |
DBLP DOI BibTeX RDF |
partitioning, parallel loops, iteration space |
| 1 | Jayram Moorkanikara Nageswaran, Nikil Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum |
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. |
IJCNN |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal |
Improving SDRAM access energy efficiency for low-power embedded systems. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
embedded processors and low power, fetch buffer, write-combining buffer, SDRAM |
| 1 | José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum |
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. |
IJES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan L. Aragón, Alexander V. Veidenbaum |
Optimizing CAM-based instruction cache designs for low-power embedded systems. |
Journal of Systems Architecture - Embedded Systems Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum |
A centralized cache miss driven technique to improve processor power dissipation. |
ICSAMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Xinmin Tian, Milind Girkar, Hideki Saito, Utpal Banerjee |
Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor. |
ICSAMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero |
A Two-Level Load/Store Queue Based on Execution Locality. |
ISCA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero |
A distributed processor state management architecture for large-window processors. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dynamic resizing, performance, embedded processor, register file |
| 1 | Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. |
CASES |
2008 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power |
| 1 | Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum |
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot |
Adaptive techniques for leakage power management in L2 cache peripheral circuits. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos |
Cache-aware iteration space partitioning. |
PPOPP |
2008 |
DBLP DOI BibTeX RDF |
load balancing, caches |
| 1 | Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum |
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. |
LCTES |
2008 |
DBLP DOI BibTeX RDF |
superoperators, embedded systems, java virtual machine, energy estimation, profile-guided optimization |
| 1 | Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. |
LCTES |
2008 |
DBLP DOI BibTeX RDF |
energy-delay, out-of-order embedded processor, resource resizing, performance, architecture |
| 1 | Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau |
A predictive decode filter cache for reducing power consumption in embedded processors. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Cache, embedded processors, power optimization |
| 1 | Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum |
A simplified java bytecode compilation system for resource-constrained embedded processors. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
superoperators, embedded systems, java virtual machine, adaptive optimization, profile-guided optimization |
| 1 | Jeff Furlong, Andrew Felch, Jayram Moorkanikara Nageswaran, Nikil Dutt, Alex Nicolau, Alexander V. Veidenbaum, Ashok Chandrashekar, Richard Granger |
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. |
PARCO |
2007 |
DBLP BibTeX RDF |
|
| 1 | Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum |
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. |
SIGMETRICS |
2007 |
DBLP DOI BibTeX RDF |
SPEC CPU benchmarks, performance evaluation, caches, branch prediction |
| 1 | Houman Homayoun, Alexander V. Veidenbaum |
Reducing leakage power in peripheral circuits of L2 caches. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li 0015, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos |
Tight analysis of the performance potential of thread speculation using spec CPU 2006. |
PPOPP |
2007 |
DBLP DOI BibTeX RDF |
conflict probability, misspeculation penalty, threading overhead, performance evaluation, speculative execution |
| 1 | Milind Girkar, Arun Kejariwal, Xinmin Tian, Hideki Saito, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos |
Probablistic Self-Scheduling. |
Euro-Par |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Kejariwal, Xinmin Tian, Wei Li 0015, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos |
On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. |
ICS |
2006 |
DBLP DOI BibTeX RDF |
DOALL loops, value dependence, performance evaluation, data dependence, speculative execution, control dependence |
| 1 | Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum |
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Milind Girkar, Xinmin Tian, Hideki Saito |
Challenges in exploitation of loop parallelism in embedded applications. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multithreading, multi-cores, vectorization, libraries, programming models, thread-level speculation, parallel loops |
| 1 | Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta |
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
Cache-line size adaptivity, parameterized loop nests, interference, spatial locality |
| 1 | Ana Azevedo, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau |
High performance annotation-aware JVM for Java cards. |
EMSOFT |
2005 |
DBLP DOI BibTeX RDF |
superoperators, virtual machine, high performance, Java card |
| 1 | Juan L. Aragón, Alexander V. Veidenbaum |
Energy-Effective Instruction Fetch Unit for Wide Issue Processors. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum |
An asymmetric clustered processor based on value content. |
ICS |
2005 |
DBLP DOI BibTeX RDF |
content aware architectures, cluster architectures |
| 1 | Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau |
Using a Way Cache to Improve Performance of Set-Associative Caches. |
ISHPC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Miquel Pericàs, Adrián Cristal, Rubén González, Alexander V. Veidenbaum, Mateo Valero |
Decoupled State-Execute Architecture. |
ISHPC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa |
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
Instruction Wakeup, Low Power, CAM, Issue Queue, Out-of-Order Processors |
| 1 | Alexander V. Veidenbaum |
Guest Editor's Introduction: Application-Specific Processors. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa |
A partitioned instruction queue to reduce instruction wakeup energy. |
IJHPCN |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero |
A Content Aware Integer Register File Organization. |
ISCA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau |
Caching Values in the Load Store Queue. |
MASCOTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero |
An Optimized Front-End Physical Register File with Banking and Writeback Filtering. |
PACS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu |
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum, Dan Nicolaescu |
Low Energy, Highly-Associative Cache Design for Embedded Processors. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo |
Power-Aware Compilation for Register File Energy Reduction. |
International Journal of Parallel Programming |
2003 |
DBLP DOI BibTeX RDF |
register file management, compiler support, energy aware |
| 1 | Alex Orailoglu, Alexander V. Veidenbaum |
Guest Editors' Introduction: Application-Specific Microprocessors. |
IEEE Design & Test of Computers |
2003 |
DBLP BibTeX RDF |
|
| 1 | Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau |
Reducing data cache energy consumption via cached load/store queue. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
LSQ, load queue, store queue, low power, cache, memory, low energy, low latency |
| 1 | José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez |
Energy Aware Register File Implementation through Instruction Predecode. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau |
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum |
A Data Cache with Dynamic Mapping. |
LCPC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso (eds.) |
High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings |
ISHPC |
2003 |
DBLP BibTeX RDF |
|
| 1 | Marco A. Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero |
A Simple Low-Energy Instruction Wakeup Mechanism. |
ISHPC |
2003 |
DBLP DOI BibTeX RDF |
Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window |
| 1 | Sudeep Pasricha, Alexander V. Veidenbaum |
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum |
Guest Editor's Introduction. |
International Journal of Parallel Programming |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau |
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta |
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. |
ISHPC |
2002 |
DBLP BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum |
Guest Editor's Introduction. |
International Journal of Parallel Programming |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil Kim, Alexander V. Veidenbaum |
On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors. |
The Journal of Supercomputing |
2000 |
DBLP DOI BibTeX RDF |
interconnection networks, prefetching, weak consistency |
| 1 | Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta |
Compiler-Directed Cache Line Size Adaptivity. |
Intelligent Memory Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta |
Compiler-Directed Cache Assist Adaptivity. |
ISHPC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward H. Gornish, Alexander V. Veidenbaum |
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. |
International Journal of Parallel Programming |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum, Qingbo Zhao, Abduhl Shameer |
Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors. |
International Journal of High Speed Computing |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil Kim, Alexander V. Veidenbaum |
Interconnection network organization and its impact on performance and cost in shared memory multiprocessors. |
Parallel Computing |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau, Xiaomei Ji |
Adapting cache line size to application behavior. |
International Conference on Supercomputing |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle Gallivan |
Retrospective: The Cedar System. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
Cedar |
| 1 | Sunil Kim, Alexander V. Veidenbaum |
The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems. |
IEEE PACT |
1997 |
DBLP DOI BibTeX RDF |
software cache coherence, interconnection network, prefetching, shared memory systems, network bandwidth, weak consistency |
| 1 | Sunil Kim, Alexander V. Veidenbaum |
Stride-directed Prefetching for Secondary Caches. (PDF / PS) |
ICPP |
1997 |
DBLP DOI BibTeX RDF |
Secondary Caches, Stride Detection, Memory Hierarchy, Data Prefetching |
| 1 | Alexander V. Veidenbaum |
Instruction Cache Prefetching Using Multilevel Branch Prediction. |
ISHPC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Elana D. Granston, Alexander V. Veidenbaum |
Combining flow and dependence analyses to expose redundant array accesses. |
International Journal of Parallel Programming |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil Kim, Alexander V. Veidenbaum |
On Shortest Path Routing in Single Stage Shuffle-Exchange Networks. |
SPAA |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen W. Turner, Alexander V. Veidenbaum |
Scalability of the Cedar system. |
SC |
1994 |
DBLP BibTeX RDF |
|
| 1 | Edward H. Gornish, Alexander V. Veidenbaum |
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. |
ICPP |
1994 |
DBLP BibTeX RDF |
|
| 1 | David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner |
The Cedar System and an Initial Performance Study. |
ISCA |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Chin Chen, Alexander V. Veidenbaum |
Performance Evaluation of Memory Caches in Multiprocessors. |
ICPP |
1993 |
DBLP BibTeX RDF |
|
| 1 | Yung-Chin Chen, Alexander V. Veidenbaum |
An Effective Write Policy for Software Coherence Schemes. |
SC |
1992 |
DBLP BibTeX RDF |
|
| 1 | Elana D. Granston, Alexander V. Veidenbaum |
Detecting redundant accesses to array data. |
SC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Chin Chen, Alexander V. Veidenbaum |
Comparison and analysis of software and directory coherence schemes. |
SC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | John D. Bruner, Hoichi Cheong, Alexander V. Veidenbaum, Pen-Chung Yew |
Chief: A Parallel Simulation Environment for Parallel Systems. |
IPPS |
1991 |
DBLP BibTeX RDF |
|
| 1 | Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter |
The Organization of the Cedar System. |
ICPP |
1991 |
DBLP BibTeX RDF |
|
| 1 | Kyle Gallivan, William Jalby, Stephen W. Turner, Alexander V. Veidenbaum, Harry A. G. Wijshoff |
Preliminary Performance Analysis of the Cedar Multiprocessor Memory System. |
ICPP |
1991 |
DBLP BibTeX RDF |
|
| 1 | Elana D. Granston, Alexander V. Veidenbaum |
An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems. |
ICPP |
1991 |
DBLP BibTeX RDF |
|
| 1 | Yung-Chin Chen, Alexander V. Veidenbaum |
A software coherence scheme with the assistance of directories. |
ICS |
1991 |
DBLP DOI BibTeX RDF |
RISC |
| 1 | Hoichi Cheong, Alexander V. Veidenbaum |
Compiler-Directed Cache Management in Multiprocessors. |
IEEE Computer |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum |
Compiler-directed data prefetching in multiprocessors with memory hierarchies. |
ICS |
1990 |
DBLP DOI BibTeX RDF |
FORTRAN |
| 1 | Hoichi Cheong, Alexander V. Veidenbaum |
A version control approach to Cache coherence. |
ICS |
1989 |
DBLP DOI BibTeX RDF |
parallel task execution, software-directed cache coherence, version control |
| 1 | Hoichi Cheong, Alexander V. Veidenbaum |
A Cache Coherence Scheme With Fast Selective Invalidation. |
ISCA |
1988 |
DBLP BibTeX RDF |
|
| 1 | Hoichi Cheong, Alexander V. Veidenbaum |
Stale Data Detection and Coherence Enforcement Using Flow Analysis. |
ICPP |
1988 |
DBLP BibTeX RDF |
|
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