Search results for "Ali Ahmadinia"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michael Opoku Agyeman, Ali Ahmadinia	Power and area optimisation in heterogeneous 3D networks-on-chip architectures.	SIGARCH Computer Architecture News	2011	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Hernando Fernandez-Canque	Optimization of reconfigurable multi-core system-on-chips for multi-standard applications.	KES Journal	2011	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Alireza Shahrabi	A Highly Adaptive and Efficient Router Architecture for Network-on-Chip.	Comput. J.	2011	DBLP DOI BibTeX RDF
1	Michael Opoku Agyeman, Ali Ahmadinia	Optimising Heterogeneous 3D Networks-on-Chip.	PARELEC	2011	DBLP DOI BibTeX RDF
1	Hernando Fernandez-Canque, Sorin Hintea, Roberto Ramirez-Iniguez, Ali Ahmadinia, Gabor Csipkes, Doris Csipkes	Machine Vision Applied to Highly Variable Objects.	KES	2011	DBLP DOI BibTeX RDF
1	Roberto Ramirez-Iniguez, Ali Ahmadinia, Hernando Fernandez-Canque	DTIRC Based Optical Collimators.	KES	2011	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Hernando Fernandez-Canque, Roberto Ramirez-Iniguez	Dynamic Reconfiguration in JPEG2000 Hardware Architecture.	KES	2011	DBLP DOI BibTeX RDF
1	Ali Shahrabi, Ali Ahmadinia	An Efficient Router Architecture for Network on Chip.	PECCS	2011	DBLP BibTeX RDF
1	Balal Ahmad, Ali Ahmadinia, Tughrul Arslan	High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen	ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Alireza Shahrabi	Adaptive Router Architecture for Optimising Quality of Service in Networks-on-Chip.	CIT	2010	DBLP DOI BibTeX RDF	Networks-on-Chip
1	Ali Ahmadinia, Tughrul Arslan, Hernando Fernandez-Canque	Optimization of Reconfigurable Multi-core SOCs for Multi-standard Applications.	KES	2009	DBLP DOI BibTeX RDF
1	Hernando Fernandez-Canque, Sorin Hintea, John Freer, Ali Ahmadinia	Machine Vision Application to Automatic Intruder Detection Using CCTV.	KES	2009	DBLP DOI BibTeX RDF	CCTV, human posture recognition, image processing, Machine vision
1	Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich	Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Balal Ahmad, Tughrul Arslan	Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Balal Ahmad, Tughrul Arslan	Efficient High-Level Power Estimation for Multi-standard Wireless Systems.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan	SystemC-based Custom Reconfigurable Cores for Wireless Applications.	ERSA	2008	DBLP BibTeX RDF
1	Ali Ahmadinia	Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	free-space manager, routing-conscious placement, line-sweep technique, optimal runtime, field-programmable gate array (FPGA), lower bounds, Reconfigurable hardware, geometric optimization, module placement
1	Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda	The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	FPGA-based computer, rekonfiguration manager, platform, relocation, partiall dynamic reconfiguration, ESM
1	Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan	System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Balal Ahmad, Tughrul Arslan	System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design.	AHS	2007	DBLP DOI BibTeX RDF
1	Balal Ahmad, Ali Ahmadinia, Tughrul Arslan	Hybrid Communication Medium for Adaptive SoC Architectures.	AHS	2007	DBLP DOI BibTeX RDF
1	Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan	Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ali Ahmadinia	Optimization algorithms for dynamically reconfigurable embedded systems.		2006	RDF
1	Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich	A Flexible Reconfiguration Manager for the Erlangen Slot Machine.	ARCS Workshops	2006	DBLP BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Jürgen Teich	Online placement for dynamically reconfigurable devices.	IJES	2005	DBLP DOI BibTeX RDF
1	Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen	DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices	CoRR	2005	DBLP BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen	A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices	CoRR	2005	DBLP BibTeX RDF
1	Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich	Defragmenting the Module Layout of a Partially Reconfigurable Device	CoRR	2005	DBLP BibTeX RDF
1	Christophe Bobda, Ali Ahmadinia	Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	Dynamic Interconnection, Network on Chip, Reconfigurable Hardware
1	Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen	DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.	FPL	2005	DBLP BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen	A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru	Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs.	ARCS Workshops	2005	DBLP BibTeX RDF
1	Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich	Defragmenting the Module Layout of a Partially Reconfigurable Device.	ERSA	2005	DBLP BibTeX RDF
1	Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich	The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms.	FPT	2005	DBLP BibTeX RDF
1	Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich	Packet Routing in Dynamically Changing Networks on Chip.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen	The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.	FCCM	2005	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen	Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices	CoRR	2004	DBLP BibTeX RDF
1	Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich	A Dynamic NoC Approach for Communication in Reconfigurable Devices.	FPL	2004	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen	Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.	FPL	2004	DBLP DOI BibTeX RDF	field-programable gate array (FPGA), occupied space manager (OSM), routing-conscious placement, Manhattan metric, line sweep technique, optimal running time, lower bounds, Reconfigurable computing, module placement
1	Ali Ahmadinia	Optimization Algorithms for Dynamic Reconfigurable Embedded Systems p.	FPL	2004	DBLP DOI BibTeX RDF
1	Christophe Bobda, Ali Ahmadinia, Jürgen Teich	Generation of Distributed Arithmetic Designs for Reconfigurable Application.	ARCS Workshops	2004	DBLP BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Jürgen Teich	A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware.	ARCS	2004	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich	Task scheduling for heterogeneous reconfigurable computers.	SBCCI	2004	DBLP DOI BibTeX RDF	hardware preemption, scheduling, FPGA, placement, reconfigurable computing, partial reconfiguration
1	Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich	Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.	IPDPS	2004	DBLP DOI BibTeX RDF	Virtex, Compression, Decompression
1	Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich	A New Approach for On-line Placement on Reconfigurable Devices.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Jürgen Teich	Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead.	VLSI-SOC	2003	DBLP BibTeX RDF

Publications of "Ali Ahmadinia" ( http://dblp.L3S.de/Authors/Ali_Ahmadinia )