Search results for "Ali Jahanian"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Marzieh Morshedzadeh Morshedzadeh, Ali Jahanian	Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Sirvan Khalighi, Somayeh Maabi, Mercedeh Sanjabi, Ali Jahanian	Landmark-based Car Navigation with Overtake Capability in Multi-agent Environments.	ICAART	2012	DBLP BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh	Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology.	Integration	2011	DBLP DOI BibTeX RDF
1	Zohre Mohammadi-Arfa, Ali Jahanian	A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Adel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi, M. Taghi Teimoori	Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Behzad Salami, Morteza Saheb Zamani, Ali Jahanian	VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs.	DSD	2011	DBLP DOI BibTeX RDF
1	Mehdi Alipour, Mohammad Haji Seyed Javadi, Ali Jahanian	Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani	Early Buffer Planning with Congestion Control Using Buffer Requirement Map.	Journal of Circuits, Systems, and Computers	2010	DBLP DOI BibTeX RDF
1	Mercedeh Sanjabi, Somayeh Maabi, Zahra Esmaeili, Ali Jahanian, Sirvan Khalighi	A Landmark-Based Navigation System for High Speed Cars in the Roads with Branches.	I. J. Information Acquisition	2009	DBLP DOI BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani	Improved performance and yield with chip master planning design methodology.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip planning, highway on chip, interconnect planning
1	Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani	Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.	DATE	2009	DBLP BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani	Using metro-on-chip in physical design flow for congestion and routability improvement.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF
1	Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani	Performance Improvement of Physical Retiming with Shortcut Insertion.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani	Performance and Timing Yield Enhancement using Highway-on-Chip Planning.	DSD	2008	DBLP DOI BibTeX RDF
1	Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian	Evaluation, prediction and reduction of routing congestion.	Microelectronics Journal	2007	DBLP DOI BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani	Improved timing closure by early buffer planning in floor-placement design flow.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, design convergence, buffer insertion
1	Ali Jahanian, Morteza Saheb Zamani	Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF	Buffer planning, incremental placement, buffer insertion
1	Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian	Prediction and reduction of routing congestion.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, congestion, routability
1	Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari	Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms.	DSD	2005	DBLP DOI BibTeX RDF
1	Mohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi	Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.	DSD	2004	DBLP DOI BibTeX RDF

Publications of "Ali Jahanian" ( http://dblp.L3S.de/Authors/Ali_Jahanian )