Search results for "Alper Buyuktosunoglu"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	CPU Accounting for Multicore Processors.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger	Power management of multi-core chips: Challenges and pitfalls.	DATE	2012	DBLP BibTeX RDF
1	Augusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff H. Derby, Michele Franceschini, Charles Johnson, Robert K. Montoye	Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor.	HPCA	2012	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu	Introducing the Adaptive Energy Management Features of the Power7 Chip.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C. Rubio, Birgit Schubert, Bruno Spruth, José A. Tierno, Lorena Pesantez	Adaptive energy-management features of the IBM POWER7 chip.	IBM Journal of Research and Development	2011	DBLP DOI BibTeX RDF
1	Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer	Abstraction and microarchitecture scaling in early-stage power modeling.	HPCA	2011	DBLP DOI BibTeX RDF
1	Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram	A case for guarded power gating for multi-core processors.	HPCA	2011	DBLP DOI BibTeX RDF
1	Ruhi Sarikaya, Alper Buyuktosunoglu	A Unified Prediction Method for Predicting Program Behavior.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Microprocessor performance phase prediction, adaptive dynamic management, application program phase prediction
1	Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram	Guarded Power Gating in a Multi-core Setting.	ISCA Workshops	2010	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose	Power and thermal characterization of POWER6 system.	PACT	2010	DBLP DOI BibTeX RDF
1	Victor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Trends and techniques for energy efficient architectures.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban	Power-efficient, reliable microprocessor architectures: modeling and design methods.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power-efficient design, pre-silicon modeling, reliable operation
1	Ruhi Sarikaya, Canturk Isci, Alper Buyuktosunoglu	Program behavior prediction using a statistical metric model.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	system performance measurement, monitoring and forecasting, computer architecture, workload characterization
1	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	CPU Accounting in CMP Processors.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
1	Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin	Dynamic power gating with quality guarantees.	ISLPED	2009	DBLP DOI BibTeX RDF	execution units, low power, power management, microarchitecture, power gating
1	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.	PACT	2009	DBLP DOI BibTeX RDF
1	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero	Software-Controlled Priority Characterization of POWER5 Processor.	ISCA	2008	DBLP DOI BibTeX RDF
1	Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer	Exploring power management in multi-core systems.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose	Evaluating design tradeoffs in on-chip power management for CMPs.	ISLPED	2007	DBLP DOI BibTeX RDF	fetch throttling, dynamic voltage scaling, power-aware, chip multi-processor
1	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
1	Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi	An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.	MICRO	2006	DBLP DOI BibTeX RDF
1	Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi	Long-Term Workload Phases: Duration Predictions and Applications to DVFS.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Adaptive dynamic management, workload behavior, duration predictions, prediction techniques, DVFS, performance counters
1	YongKang Zhu, David H. Albonesi, Alper Buyuktosunoglu	A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.	ISPASS	2005	DBLP DOI BibTeX RDF
1	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
1	Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose	Microarchitectural techniques for power gating of execution units.	ISLPED	2004	DBLP DOI BibTeX RDF	execution units, low power, microarchitecture, power-gating
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
1	David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster	Dynamically Tuning Processor Resources with Adaptive Processing.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu	Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.	PACS	2003	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster	Tradeoffs in power-efficient issue queue design.	ISLPED	2002	DBLP DOI BibTeX RDF	non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue
1	Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott	Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.	PACS	2002	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook	A circuit level implementation of an adaptive issue queue for power-aware microprocessors.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
1	Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi	Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.	VLSI-SOC	2001	DBLP BibTeX RDF
1	David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.	IEEE Micro	2000	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.	MICRO	2000	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi	An Adaptive Issue Queue for Reduced Power at High Performance.	PACS	2000	DBLP DOI BibTeX RDF

Publications of "Alper Buyuktosunoglu" ( http://dblp.L3S.de/Authors/Alper_Buyuktosunoglu )