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Publications of "Anant Vishnoi" ( http://dblp.L3S.de/Authors/Anant_Vishnoi )

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Publication years (Num. hits)
2009 (2) 2010 (1) 2011 (1)
Publication types (Num. hits)
article(1) inproceedings(3)
Venues (Conferences, Journals, ...)
DAC(1) DATE(1) IEEE Trans. Computers(1) VLSI-SoC(1)
Authors
Anant Vishnoi(4) M. Balakrishnan(4) Preeti Ranjan Panda(4)
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Found 4 publication records. Showing 4 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi Compressing Cache State for Postsilicon Processor Debug. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan Enhancing post-silicon processor debug with Incremental Cache state Dumping. Search on Bibsonomy VLSI-SoC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan Online cache state dumping for processor debug. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cache compression, processor debug, silicon debug, design for debug, post-silicon validation
1Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan Cache aware compression for processor debug support. Search on Bibsonomy DATE The full citation details ... 2009 DBLP  BibTeX  RDF
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