| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, Andre Ivanov |
Lazy suspect-set computation: fault diagnosis for deep electrical bugs.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov |
Self-checking test circuits for latches and flip-flops. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Erno Salminen, Cristian Grecu, Timo D. Hämäläinen, André Ivanov |
Application modelling and hardware description for network-on-chip benchmarking. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Faizal Karim, Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Konrad Walus, André Ivanov, Fabrizio Lombardi |
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. |
J. Electronic Testing |
2009 |
DBLP DOI BibTeX RDF |
Quantum-dot cellular automata (QCA), Clocked QCA, Emerging nanotechnologies, Phase shift |
| 1 | Rod Blaine Foist, Cristian Grecu, André Ivanov, Robin Turner |
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic. |
IEEE Trans. Education |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, André Ivanov |
Novel interconnect infrastructures for massive multicore chips - an overview. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande |
Testing Network-on-Chip Communication Fabrics. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Baosheng Wang, Yuejian Wu, André Ivanov |
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young |
Test scheduling for built-in self-tested embedded SRAMs with data retention faults. |
IET Computers & Digital Techniques |
2007 |
DBLP BibTeX RDF |
|
| 1 | Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov |
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. |
Integration |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu |
Towards Open Network-on-Chip Benchmarks. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
performance evaluation, metrics, benchmarks, networks-on-chip |
| 1 | Marco Ottavi, Hamid Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov |
On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh |
Essential Fault-Tolerance Metrics for NoC Infrastructures. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov |
Fast detection of data retention faults and other SRAM cell open defects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
BIST for Network-on-Chip Interconnect Infrastructures. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip |
| 1 | André Ivanov |
Session Abstract. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuejian Wu, André Ivanov |
Low Power SoC Memory BIST. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande |
NoC Interconnect Yield Improvement Using Crosspoint Redundancy. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande |
On-line Fault Detection and Location for NoC Interconnects. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
Timing analysis of network on chip architectures for MP-SoC platforms. |
Microelectronics Journal |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh |
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP |
| 1 | Andy Kuo, Roberto Rosales, Touraj Farahmand, Sassan Tabatabaei, André Ivanov |
Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects. |
IEEE T. Instrumentation and Measurement |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yvan Maidon, Thomas Zimmer, André Ivanov |
An Analog Circuit Fault Characterization Methodology. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
analog circuit testing, analog fault diagnosis, analog fault characterization |
| 1 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
| 1 | Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli |
Design, Synthesis, and Test of Networks on Chips. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
Reliability, VLSI, Automatic synthesis, VLSI Systems, Testing and Fault-Tolerance |
| 1 | André Ivanov, Giovanni De Micheli |
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
micronetworks, networks on chips, multiprocessor SoCs, on-chip interconnection network, on-chip communication, infrastructure IP |
| 1 | Touraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov |
A DDJ calibration methodology for high-speed test and measurement equipments. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov |
A retention-aware test power model for embedded SRAM. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
data retention fault test, multiple embedded SRAMs, test power modeling, test scheduling |
| 1 | Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian |
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
Data Retention Faults, Zero-time DRF Testing, Opens, Embedded SRAMs |
| 1 | Baosheng Wang, Yuejian Wu, André Ivanov |
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh |
Effect of traffic localization on energy dissipation in NoC-based interconnect. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov |
A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov |
A 0.35µm CMOS comparator circuit for high-speed ADC applications. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh |
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohsen Nahvi, André Ivanov |
Indirect test architecture for SoC testing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov |
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects. |
IEEE Design & Test of Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov, Fabrizio Lombardi, Cecilia Metra |
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates. (PDF / PS) |
IEEE Design & Test of Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
A Scalable Communication-Centric SoC Interconnect Architecture. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure |
| 1 | Andy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei |
Jitter Models and Measurement Methods for High-Speed Serial Interconnects. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
BFT, scalability, pipelining, bus, MP-SoC |
| 1 | Josep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov |
Sensing temperature in CMOS circuits for Thermal Testing. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
analysis failure, built-in self test, Thermal testing, temperature sensors |
| 1 | Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian |
Reducing Embedded SRAM Test Time under Redundancy Constraints. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
Memory Test Time, Memory Redundancy, Memory testing, March Tests, Embedded SRAMs |
| 1 | Josh Yang, Baosheng Wang, André Ivanov |
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
6T SRAM, Area Penalty, Write Recovery, Memory testing, Test Time, Open Defects |
| 1 | Baosheng Wang, Yuejian Wu, André Ivanov |
Designs for Reducing Test Time of Distributed Small Embedded SRAMs. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time |
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Josep Altet, André Ivanov, A. Wong |
Thermal Testing of Analogue Integrated Circuits: A Case Study. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
test of analogue ICs, thermal analysis of ICs, built-in self-testing, CMOS technology, thermal testing |
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Guest Editorial. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei |
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. |
IEEE Design & Test of Computers |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov |
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis |
| 1 | Partha Pratim Pande, Cristian Grecu, André Ivanov |
High-Throughput Switch-Based Interconnect for Future SoCs. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture |
| 1 | Mohsen Nahvi, André Ivanov |
An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Zahra Sadat Ebadi, André Ivanov |
Time Domain Multiplexed TAM: Implementation and Comparison. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
Time domain multiplexed TAM, Optimal test time, Test Access Mechanism (TAM), SoC testing, Embedded core testing |
| 1 | Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh |
Design of a switch for network on chip applications. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov |
Analog IP design flow for SoC applications. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Baosheng Wang, Josh Yang, André Ivanov |
Reducing Test Time of Embedded SRAMs. |
MTDT |
2003 |
DBLP DOI BibTeX RDF |
Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time |
| 1 | Ashish Syal, Victor Lee, André Ivanov, Josep Altet |
CMOS Differential and Absolute Thermal Sensors. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
differential thermal sensors, absolute thermal sensors, IDDQ, thermal testing |
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Test Technology Technical Council Newsletter. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sassan Tabatabaei, André Ivanov |
Embedded Timing Analysis: A SoC Infrastructure. |
IEEE Design & Test of Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sassan Tabatabaei, André Ivanov |
An Embedded Core for Sub-Picosecond Timing Measurements. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohsen Nahvi, André Ivanov, Resve A. Saleh |
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Bartomeu Alorda, André Ivanov, Jaume Segura |
An Off-Chip Sensor Circuit for On-Line Transient Current Testing. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand |
On the detectability of CMOS floating gate transistor faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov |
Test Technology Newsletter. |
J. Electronic Testing |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Zahra Sadat Ebadi, André Ivanov |
Design of an Optimal Test Access Architecture Using a Genetic Algorithm. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
Optimal testing time, test data width, Genetic Algorithm, Test Access Mechanism (TAM), SOC testing, Embedded core testing |
| 1 | Ashish Syal, Victor Lee, André Ivanov, Josep Altet |
CMOS Differential and Absolute Thermal Sensors. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov, Vikram Devdas |
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study. |
J. Electronic Testing |
2000 |
DBLP DOI BibTeX RDF |
current mode logic (CML), CML circuit testing, bipolar circuit testing, catastrophic fault detection, defect-based testing |
| 1 | Fidel Muradali, André Ivanov |
Do I Need this Tool for My Chips to Work? |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Bapiraju Vinnakota, André Ivanov |
Biomedical ICs: What is Different about Testing those ICs? |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq |
Optimal conditions for Boolean and current detection of floating gate faults. |
ITC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sassan Tabatabaei, André Ivanov |
A Current Integrator for BIST of Mixed-Signal ICs. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sassan Tabatabaei, André Ivanov |
A built-in current monitor for testing analog circuit blocks. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell |
Testing for Floating Gates Defects in CMOS Circuits. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram Devdas, André Ivanov |
Non-Intrusive Testing of High-Speed CML Circuits. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand |
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Maneesha Dalmia, André Ivanov, Sassan Tabatabaei |
Power supply current monitoring techniques for testing PLLs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs |
| 1 | André Ivanov, Barry K. Tsuji, Yervant Zorian |
Programmable BIST Space Compactors. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
BIST methodologies, BIST space compaction, parity tree, BIST compaction, genetic algorithms, Testing, Built-In Self-Test (BIST), design for testability |
| 1 | Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov |
Panel Summaries. |
IEEE Design & Test of Computers |
1996 |
DBLP BibTeX RDF |
|
| 1 | Yuejian Wu, André Ivanov |
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST. |
IEEE Trans. Computers |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Lambidonis, André Ivanov, Vinod K. Agarwal |
Fast signature computation for BIST linear compactors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier |
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes. |
J. Electronic Testing |
1995 |
DBLP DOI BibTeX RDF |
compact testing, multiple signature analysis, Built-in self-test, fault simulation, fault coverage, signature analysis |
| 1 | Yuejian Wu, André Ivanov |
Reducing Hardware with Fuzzy Multiple Signature Analysis. |
IEEE Design & Test of Computers |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Bishop, André Ivanov |
Fault Simulation of an OTA Biquadratic Filter. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Slawomir Pilarski, André Ivanov, Tiko Kameda |
On minimizing aliasing in scan-based compaction. |
J. Electronic Testing |
1994 |
DBLP DOI BibTeX RDF |
built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, scan path, test response compaction |
| 1 | A. J. Bishop, André Ivanov |
On the Testability of CMOS Feedback Amplifiers. |
DFT |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiko Kameda, Slawomir Pilarski, André Ivanov |
Notes on Multiple Input Signature Analysis. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
multiple input signature analysis, multiple-input compactors, error assumptions, binary memory elements, standard linear algebra notions, logic testing, probability, built-in self test, feedback, aliasing, shift registers, VLSI circuits, error model, irreducible polynomial |
| 1 | Slawomir Pilarski, Tiko Kameda, André Ivanov |
Sequential faults and aliasing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Yervant Zorian, André Ivanov |
Programmable Space Compaction for BIST. |
FTCS |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Yervant Zorian, André Ivanov |
An Effective BIST Scheme for ROM's. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov, Yervant Zorian |
Count-based BIST compaction schemes and aliasing probability computation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal |
Using an asymmetric error model to study aliasing in signature analysis registers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams |
Iterative algorithms for computing aliasing probabilities. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Lambidonis, André Ivanov, Vinod K. Agarwal |
Fast Signature Computation for Linear Compactors. |
ITC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Yervant Zorian, André Ivanov |
EEODM: An effective BIST scheme for ROMs. |
ITC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | André Ivanov, Yervant Zorian |
Computing the Error Escape Probability in Count-Based Compaction Schemes. |
ICCAD |
1990 |
DBLP BibTeX RDF |
|
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