|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 7 occurrences of 7 keywords
|
|
|
|
|
Results
Found 17 publication records. Showing 17 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
Effective Robustness Analysis Using Bounded Model Checking Techniques.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Dehbashi, André Sülflow, Görschwin Fey |
Automated Design Debugging in a Testbench-Based Verification Environment. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Finder, André Sülflow, Görschwin Fey |
Latency Analysis for Sequential Circuits. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
Soft Error Analysis, f, Debugging, Sequential Circuits, Latency |
| 1 | André Sülflow |
WoLFram - a word level framework for formal verification and its application. |
|
2010 |
RDF |
|
| 1 | Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). |
it - Information Technology |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
RobuCheck: A Robustness Checker for Digital Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Rolf Drechsler |
Using QBF to increase accuracy of SAT-based debugging. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Rolf Drechsler |
Automatic Fault Localization for Programmable Logic Controllers. |
FORMS/FORMAT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Rolf Drechsler |
Towards Unifying Localization and Explanation for Automated Debugging. |
MTV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
WoLFram- A Word Level Framework for Formal Verification. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
Robustness Check for Multiple Faults Using Formal Techniques. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Rolf Drechsler |
Computing bounds for fault tolerance using formal techniques. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
fault tolerance, formal verification, SAT |
| 1 | André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
Evaluation of Cardinality Constraints on SMT-Based Debugging. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
Increasing the accuracy of SAT-based debugging. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
Using unsatisfiable cores to debug multiple design errors. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
sat-based debugging, unsatisfiable core, fault localization |
| 1 | André Sülflow, Rolf Drechsler |
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Nicole Drechsler, Rolf Drechsler |
Robust Multi-Objective Optimization in High Dimensional Spaces. |
EMO |
2006 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #17 of 17 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")