| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm |
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici |
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, Andre Ivanov |
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita |
Automated data analysis techniques for a modern silicon debug environment. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita |
On error tolerance and Engineering Change with Partially Programmable Circuits. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zissis Poulos, Yu-Shen Yang, Jason Anderson, Andreas G. Veneris, Bao Le |
Leveraging reconfigurability to raise productivity in FPGA functional debug. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris |
Non-solution implications using reverse domination in a modern SAT-based debugging environment. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton |
Automating Logic Transformations With Approximate SPFDs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
Two-Stage, Pipelined Register Renaming. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Brian Keng, Sean Safarpour |
From RTL to silicon: The case for automated debug. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian Keng, Andreas G. Veneris |
Managing complexity in design debugging with sequential abstraction and refinement. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian Keng, Sean Safarpour, Andreas G. Veneris |
Automated debugging of SystemVerilog assertions. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour |
Debugging with dominance: On-the-fly RTL debug solution implications. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti |
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
k-induction, sequential ATPG, SAT, QBF, design debugging, BMC |
| 1 | Brian Keng, Sean Safarpour, Andreas G. Veneris |
Bounded Model Debugging. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris |
Automated Design Debugging With Maximum Satisfiability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour |
Automated silicon debug data analysis techniques for a hardware data acquisition environment. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris, Farid N. Najm |
Managing verification error traces with bounded model debugging. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus |
Leveraging dominators for preprocessing QBF. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Brian Keng, Andreas G. Veneris, Sean Safarpour |
An Automated Framework for Correction and Debug of PSL Assertions. |
MTV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris |
Automated Design Debugging With Abstraction and Refinement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. |
ICSAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris |
Automated debugging with high level abstraction and refinement. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian Keng, Andreas G. Veneris |
Scaling VLSI design debugging with interpolation. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques Silva |
Spatial and temporal design debug using partial MaxSAT. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
maximum satisfiability, design debugging |
| 1 | Andreas G. Veneris, Sean Safarpour |
The day Sherlock Holmes decided to do EDA. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
error localization, verification, debugging |
| 1 | Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris |
Automated data analysis solutions to silicon debug. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith |
Sequential logic rectifications with approximate SPFDs. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
Improved SAT-based Reachability Analysis with Observability Don't Cares. |
JSAT |
2008 |
DBLP BibTeX RDF |
|
| 1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
A physical level study and optimization of CAM-based checkpointed register alias table. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian Keng, Hratch Mangassarian, Andreas G. Veneris |
A succinct memory model for automated design debugging. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni |
On the latency, energy and area of checkpointed, superscalar register alias tables. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
latency, checkpointing, energy, register renaming |
| 1 | Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah |
Improved Design Debugging Using Maximum Satisfiability. |
FMCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton |
Automating Logic Rectification by Approximate SPFDs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
SAT-based algorithm, approximate SPFD, digital VLSI cycle, incremental rewiring-based optimization operations, automated logic rectification tools, predefined logic transformations, memory/time explosion problem, design errors |
| 1 | Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian |
Trace Compaction using SAT-based Reachability Analysis. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir |
Maximum circuit activity estimation using pseudo-boolean satisfiability. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris |
Abstraction and refinement techniques in automated design debugging. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith |
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman |
Extraction error modeling and automated model debugging in high-performance custom designs. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
Seamless Integration of SER in Rewiring-Based Design Space Exploration. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
L-CBF: a low-power, fast counting bloom filter architecture. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
counting bloom filters, energy per operation, delay, processors |
| 1 | Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan |
Efficient SAT-based Boolean matching for FPGA technology mapping. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
FPGA technology mapping, Boolean satisfiability, Boolean matching |
| 1 | Andreas G. Veneris, Yiorgos Makris |
Session Abstract. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
On the relation between simulation-based and SAT-based diagnosis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
Integrating observability don't cares in all-solution SAT solvers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris |
Abstraction and Refinement Techniques in Automated Design Debugging. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas |
Fault diagnosis and logic debugging using Boolean satisfiability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Brandon Liu, Andreas G. Veneris |
Incremental fault diagnosis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Jiang Brandon Liu |
Incremental Design Debugging in a Logic Synthesis Environment. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
simulation, VLSI, CAD, debugging, design error |
| 1 | Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi |
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. |
J. Electronic Testing |
2005 |
DBLP DOI BibTeX RDF |
diagnostic test generation, VLSI, test generation, fault |
| 1 | Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler |
Utilizing don't care states in SAT-based bounded sequential problems. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
don't care states, unreachable states, satisfiability, bounded model checking, sequential equivalence checking |
| 1 | Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour |
Diagnosing multiple transition faults in the absence of timing information. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
diagnosis, multiple faults, delay faults, incremental, transition faults |
| 1 | Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman |
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
Post-Verification Debugging of Hierarchical Designs. |
MTV |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
Post-verification debugging of hierarchical designs. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Andreas G. Veneris |
Logic Rewiring for Delay and Power Minimization. |
J. Inf. Sci. Eng. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Alexander Smith, Andreas G. Veneris, Anastasios Viglas |
Design diagnosis using Boolean satisfiability. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee |
Managing Don't Cares in Boolean Satisfiability. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri |
Fault equivalence and diagnostic test generation using ATPG. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith |
Debugging Sequential Circuits Using Boolean Satisfiability. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir |
Debugging sequential circuits using Boolean satisfiability. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris |
Extraction Error Diagnosis and Correction in High-Performance Designs. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris |
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. |
MTV |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris |
Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. |
MTV |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Magdy S. Abadir |
Design rewiring using ATPG. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri |
Design Rewiring Using ATPG. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi |
Incremental Diagnosis of Multiple Open-Interconnects. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir |
Incremental Diagnosis and Correction of Multiple Faults and Errors. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Mandana Amiri, Andreas G. Veneris, Ivor Ting |
Design rewiring for power minimization [logic design]. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Magdy S. Abadir, Ivor Ting |
Design rewiring based on diagnosis techniques. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Ibrahim N. Hajj |
Design error diagnosis and correction via test vector simulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs |
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Ibrahim N. Hajj |
Correcting multiple design errors in digital VLSI circuits. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Veneris, Ibrahim N. Hajj |
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. |
Great Lakes Symposium on VLSI |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Lefteris M. Kirousis, Andreas G. Veneris |
Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. |
Acta Inf. |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Lefteris M. Kirousis, Andreas G. Veneris |
Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. |
WDAG |
1993 |
DBLP DOI BibTeX RDF |
|
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