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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18 occurrences of 14 keywords
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Results
Found 39 publication records. Showing 39 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Parisa Razaghi, Andreas Gerstlauer |
Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets.  |
Embedded Systems Letters  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Parisa Razaghi, Andreas Gerstlauer |
Automatic timing granularity adjustment for host-compiled software simulation. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi |
Abstract system-level models for early performance and power exploration. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Lin, Akshaya Srivatsa, Andreas Gerstlauer, Brian L. Evans |
Heterogeneous multiprocessor mapping for real-time streaming systems. |
ICASSP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn |
A high-performance, low-power linear algebra core. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer |
Multi-core parallel simulation of System-level Description Languages. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Parisa Razaghi, Andreas Gerstlauer |
Host-compiled multicore RTOS simulator for embedded real-time software development. |
DATE |
2011 |
DBLP BibTeX RDF |
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| 1 | Ku He, Andreas Gerstlauer, Michael Orshansky |
Controlled timing-error acceptance for low energy IDCT design. |
DATE |
2011 |
DBLP BibTeX RDF |
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| 1 | Dylan Pfeifer, Andreas Gerstlauer |
Expression-Level Parallelism for Distributed Spice Circuit Simulation. |
DS-RT |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ahmed Abdel-Hadi, Jonas Michel, Andreas Gerstlauer, Sriram Vishwanath |
Real-Time Optimization of Video Transmission in a Network of AAVs. |
VTC Fall |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Gunar Schirner, Andreas Gerstlauer, Rainer Dömer |
Fast and accurate processor models for efficient MPSoC design. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich |
A system-level synthesis approach from formal application models to generic bus-based MPSoCs. |
ICSAMOS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Andreas Gerstlauer |
Host-compiled simulation of multi-core platforms. |
International Symposium on Rapid System Prototyping |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Andreas Gerstlauer |
Host-compiled simulation of multi-core platforms. |
International Symposium on Rapid System Prototyping |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Gunar Schirner, Andreas Gerstlauer, Rainer Dömer |
System-level development of embedded software. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Andreas Gerstlauer, Gunar Schirner |
Platform modeling for exploration and synthesis. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor Stefanov, Daniel D. Gajski, Jürgen Teich |
Electronic System-Level Synthesis Methodologies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller 0003 |
Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Amal Banerjee, Andreas Gerstlauer |
Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices. |
IESS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ardavan Pedram, David Craven, Andreas Gerstlauer |
Modeling Cache Effects at the Transaction Level. |
IESS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski |
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. |
EURASIP J. Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski |
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, A. Nakamura, Dai Araki, Y. Nishihara |
Specify-explore-refine (SER): from specification to implementation. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
electronic system-level (ESL) design |
| 1 | Gunar Schirner, Andreas Gerstlauer, Rainer Dömer |
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski |
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gunar Schirner, Andreas Gerstlauer, Rainer Dömer |
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig (eds.) |
Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA |
IESS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer |
Embedded Software Development in a System-Level Design Flow. |
IESS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski |
An Interactive Design Environment for C-based High-Level Synthesis. |
IESS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski |
Automatic generation of transaction level models for rapid design space exploration. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
transaction-level model, communication synthesis |
| 1 | Lukai Cai, Andreas Gerstlauer, Daniel Gajski |
Multi-metric and multi-entity characterization of applications for early system design exploration. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski |
System-level communication modeling for network-on-chip synthesis. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski |
Automatic network generation for system-on-chip communication design. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
system level design, communication synthesis |
| 1 | Lukai Cai, Andreas Gerstlauer, Daniel Gajski |
Retargetable profiling for rapid, early system-level design space exploration. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
profiling, exploration, system level design, retargetable |
| 1 | Andreas Gerstlauer, Haobo Yu, Daniel Gajski |
RTOS Modeling for System Level Design. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Haobo Yu, Andreas Gerstlauer, Daniel Gajski |
RTOS scheduling in transaction level models. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
SpecC, model, system design, RTOS |
| 1 | Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller 0003 |
The Formal Execution Semantics of SpecC. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
SpecC, simulation, formal specifications, ASMs |
| 1 | Daniel Gajski, Andreas Gerstlauer |
System-Level Abstraction Semantics. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
design semantics, modeling, methodology, system-level design, abstraction levels |
| 1 | Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann |
The Specification Language SpecC within the PARADISE Design Environment. |
DIPES |
2000 |
DBLP BibTeX RDF |
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Displaying result #1 - #39 of 39 (100 per page; Change: )
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