Search results for "Andreas Moshovos"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kaveh Aasaraai, Andreas Moshovos	NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Maryam Sadooghi-Alvandi, Kaveh Aasaraai, Andreas Moshovos	Toward virtualizing branch direction prediction.	DATE	2012	DBLP BibTeX RDF
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	Two-Stage, Pipelined Register Renaming.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic (eds.)	44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil	MICRO	2011	DBLP BibTeX RDF
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Making Address-Correlated Prefetching Practical.	IEEE Micro	2010	DBLP DOI BibTeX RDF	address-correlated prefetching, cache memories
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	On the Latency and Energy of Checkpointed Superscalar Register Alias Tables.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Andreas Moshovos, J. Gregory Steffan, Kim M. Hazelwood, David R. Kaeli (eds.)	Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010	CGO	2010	DBLP BibTeX RDF
1	Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, Andreas Moshovos	Demystifying GPU microarchitecture through microbenchmarking.	ISPASS	2010	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	Design space exploration of instruction schedulers for out-of-order soft processors.	FPT	2010	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	An Efficient Non-blocking Data Cache for Soft Processors.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors.	ICSAMOS	2009	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming.	FPL	2009	DBLP DOI BibTeX RDF
1	Ioana Burcea, Andreas Moshovos	Phantom-BTB: a virtualized branch target buffer design.	ASPLOS	2009	DBLP DOI BibTeX RDF	predictor metadata prefetching, predictor virtualization, branch target buffer
1	Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos	A tagless coherence directory.	MICRO	2009	DBLP DOI BibTeX RDF	directory coherence, cache coherence, Bloom filters
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Practical off-chip meta-data for temporal memory streaming.	HPCA	2009	DBLP DOI BibTeX RDF
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	A physical level study and optimization of CAM-based checkpointed register alias table.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Andreas Moshovos, David Tarditi, Kunle Olukotun (eds.)	17th International Conference on Parallel Architecture and Compilation Techniques (PACT 2008), Toronto, Ontario, Canada, October 25-29, 2008	PACT	2008	DBLP BibTeX RDF
1	Ioana Burcea, Stephen Somogyi, Andreas Moshovos, Babak Falsafi	Predictor virtualization.	ASPLOS	2008	DBLP DOI BibTeX RDF	predictor virtualization, caches, metadata, memory hierarchy
1	Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal instruction fetch streaming.	MICRO	2008	DBLP DOI BibTeX RDF
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal streams in commercial server applications.	IISWC	2008	DBLP DOI BibTeX RDF
1	Patrick Akl, Andreas Moshovos	Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Jason Zebchuk, Andreas Moshovos	A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Mechanisms for store-wait-free multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	store buffer design, memory consistency models
1	Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni	On the latency, energy and area of checkpointed, superscalar register alias tables.	ISLPED	2007	DBLP DOI BibTeX RDF	latency, checkpointing, energy, register renaming
1	Jason Zebchuk, Elham Safi, Andreas Moshovos	A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	MICRO	2007	DBLP DOI BibTeX RDF
1	Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi	Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays.	IEEE Micro	2006	DBLP DOI BibTeX RDF	RegionScout, region coherence arrays, coarse-grain coherence tracking, cache tag lookups, power consumption
1	Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Spatial Memory Streaming.	ISCA	2006	DBLP DOI BibTeX RDF
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	L-CBF: a low-power, fast counting bloom filter architecture.	ISLPED	2006	DBLP DOI BibTeX RDF	counting bloom filters, energy per operation, delay, processors
1	Patrick Akl, Andreas Moshovos	BranchTap: improving performance with very few checkpoints through adaptive speculation control.	ICS	2006	DBLP DOI BibTeX RDF	speculation control, state checkpointing, state recovery, branch misprediction
1	Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi	A Case for Asymmetric-Cell Cache Memories.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Andreas Moshovos	RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence.	ISCA	2005	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Alexandros Kostopoulos	Memory State Compressors for Giga-Scale Checkpoint/Restore.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Won-Ho Park, Andreas Moshovos, Babak Falsafi	RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free".	ICCD	2005	DBLP DOI BibTeX RDF
1	Amirali Baniasadi, Andreas Moshovos	SEPAS: a highly accurate energy-efficient branch predictor.	ISLPED	2004	DBLP DOI BibTeX RDF	high-performance processors, power-aware branch prediction, selective predictor access
1	Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos	Accurate and Complexity-Effective Spatial Pattern Prediction.	HPCA	2004	DBLP DOI BibTeX RDF
1	Ahmed Abdelkhalek, Angelos Bilas, Andreas Moshovos	Behavior and Performance of Interactive Multi-Player Game Servers.	Cluster Computing	2003	DBLP DOI BibTeX RDF	CPU event counters, scalability, benchmark, multi-player game, Quake
1	Navid Azizi, Farid N. Najm, Andreas Moshovos	Low-leakage asymmetric-cell SRAM.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Andreas Moshovos	Checkpointing alternatives for high performance, power-aware processors.	ISLPED	2003	DBLP DOI BibTeX RDF	checkpointing, power-aware, out-of-order execution, renaming, power density
1	Andreas Moshovos, Gurindar S. Sohi	Reducing Memory Latency via Read-after-Read Memory Dependence Prediction.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	memory dependence prediction, cache, dynamic optimization, load
1	Navid Azizi, Andreas Moshovos, Farid N. Najm	Low-leakage asymmetric-cell SRAM.	ISLPED	2002	DBLP DOI BibTeX RDF	low-leakage, low-power, SRAM, dual-Vt
1	Amirali Baniasadi, Andreas Moshovos	Asymmetric-frequency clustering: a power-aware back-end for high-performance processors.	ISLPED	2002	DBLP DOI BibTeX RDF	assymetric frequency clustering, high-performance processors, instruction criticality, processor back-end, power-aware architectures
1	Amirali Baniasadi, Andreas Moshovos	Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors.	ICCD	2002	DBLP DOI BibTeX RDF
1	Amirali Baniasadi, Andreas Moshovos	Instruction flow-based front-end throttling for power-aware high-performance processors.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi	Slice-processors: an implementation of operation-based prediction.	ICS	2001	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary	JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers.	HPCA	2001	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Gurindar S. Sohi	Memory Dependence Prediction in Multimedia Applications.	J. Instruction-Level Parallelism	2000	DBLP BibTeX RDF
1	Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee	CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit.	ISCA	2000	DBLP DOI BibTeX RDF
1	Amirali Baniasadi, Andreas Moshovos	Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors.	MICRO	2000	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Gurindar S. Sohi	Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors.	HPCA	2000	DBLP DOI BibTeX RDF	Scheduling, Cache, Memory, Instruction Level Parallelism
1	Andreas Moshovos, Gurindar S. Sohi	Speculative Memory Cloaking and Bypassing.	International Journal of Parallel Programming	1999	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Gurindar S. Sohi	Read-After-Read Memory Dependence Prediction. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	Amir Roth, Andreas Moshovos, Gurindar S. Sohi	Improving virtual function call target prediction via dependence-based pre-computation.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF
1	Amir Roth, Andreas Moshovos, Gurindar S. Sohi	Dependance Based Prefetching for Linked Data Structures.	ASPLOS	1998	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi	Dynamic Speculation and Synchronization of Data Dependences.	ISCA	1997	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Gurindar S. Sohi	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.	MICRO	1997	DBLP BibTeX RDF	DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation

Publications of "Andreas Moshovos" ( http://dblp.L3S.de/Authors/Andreas_Moshovos )