| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi |
ORION 2.0: A Power-Area Simulator for Interconnection Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai |
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuck-Boon Chan, Andrew B. Kahng |
Improved path clustering for adaptive path-delay testing. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng |
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Seokhyeong Kang |
Construction of realistic gate sizing benchmarks with known optimal solutions. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong |
MAPG: Memory access power gating. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Andrew B. Kahng, Vijayalakshmi Srinivasan |
Big Chips. |
IEEE Micro |
2011 |
DBLP DOI BibTeX RDF |
Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis |
| 1 | Andrew B. Kahng |
Roads not taken. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
Design for manufacturability: Then and now. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
The Future of Signoff. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
Product Futures. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
Roadmapping Power. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
design and test, roadmapping |
| 1 | Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu |
VLSI Physical Design - From Graph Partitioning to Timing Closure. |
|
2011 |
DOI RDF |
|
| 1 | Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong |
More realistic power grid verification based on hierarchical current and power constraints. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng |
Toward PDN resource estimation: A law of general power density. |
SLIP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Vaishnav Srinivas |
Mobile system considerations for SDRAM interface trends. |
SLIP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu |
Stability and scalability in global routing. |
SLIP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao |
Layout Decomposition Approaches for Double Patterning Lithography. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohit Gupta, Kwangok Jeong, Andrew B. Kahng |
Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao |
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, B. Lin, Kambiz Samadi |
Accurate Machine-Learning-Based On-Chip Router Modeling. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma |
Accurate Predictive Interconnect Modeling for System-Level Design. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
When is 3D 2B? |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
Scaling: More than Moore's law. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng |
Methodology from chaos in IC implementation. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang |
Toward effective utilization of timing exceptions in design optimization. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu |
Assessing chip-level impact of double patterning lithography. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng, Amirali Shayan Arani, Andrew B. Kahng, Kambiz Samadi |
Worst-case performance prediction under supply voltage and temperature variation. |
SLIP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
Recovery-driven design: a power minimization methodology for error-tolerant processor modules. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
recovery-driven design, power minimization |
| 1 | Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam |
Trace-driven optimization of networks-on-chip configurations. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
networks-on-chip, virtual channel, greedy heuristics |
| 1 | Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma |
Eyecharts: constructive benchmarking of gate sizing heuristics. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
dynamic programming, benchmarking, gate sizing |
| 1 | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
Slack redistribution for graceful degradation under voltage overscaling. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bill Lin, Kambiz Samadi |
Improved on-chip router analytical power and area modeling. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
Designing a processor from the ground up to allow voltage/reliability tradeoffs. |
HPCA |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam |
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang |
Lens aberration aware placement for timing yield. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Layout, design for manufacturing, lithography, timing yield |
| 1 | Kwangok Jeong, Andrew B. Kahng, Hailong Yao |
Revisiting the linear programming framework for leakage power vs. performance optimization. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simunic Rosing |
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu |
Is overlay error more important than interconnect variations in double patterning? |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
double patterning lithography, interconnect variations, overlay |
| 1 | Kwangok Jeong, Andrew B. Kahng |
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi |
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Mohit Gupta, Kwangok Jeong, Andrew B. Kahng |
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Andrew B. Kahng, Kambiz Samadi |
CMP Fill Synthesis: A Survey of Recent Studies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma |
Defocus-Aware Leakage Estimation and Control. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu |
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Chul-Hong Park, Xu Xu |
Fast Dual-Graph-Based Hotspot Filtering. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi |
Quantified Impacts of Guardband Reduction on Design Process Outcomes. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Guardband, chip size, yield, runtime, wirelength, design iterations |
| 1 | Andrew B. Kahng |
How to get real mad. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability |
| 1 | Puneet Gupta, Andrew B. Kahng |
Bounded-lifetime integrated circuits. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
bounded lifetime, physical IP, integrated circuits |
| 1 | Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh |
DFM in practice: hit or hype? |
DAC |
2008 |
DBLP DOI BibTeX RDF |
critical area analysis, CMP, yield, DFM, OPC, lithography |
| 1 | Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao |
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dose map, placement, timing yield, leakage power reduction |
| 1 | Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma |
Interconnect modeling for improved system-level design optimization. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester |
Investigation of diffusion rounding for post-lithography analysis. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao |
Layout decomposition for double patterning lithography. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bao Liu, Xu Xu |
Statistical Timing Analysis in the Presence of Signal-Integrity Effects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky |
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Ion I. Mandoiu, Xu Xu, Alexander Zelikovsky |
Enhanced Design Flow and Optimizations for Multiproject Wafers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park |
Detailed Placement for Enhanced Control of Resist and Etch CDs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky |
Bright-Field AAPSM Conflict Detection and Correction |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bao Liu, Qinke Wang |
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias |
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
manufacturing interface, CAD, power, flexibility, platform, design verification, multimedia design |
| 1 | Andrew B. Kahng, Rasit Onur Topaloglu |
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sherief Reda, Puneet Sharma |
On-Line Adjustable Buffering for Runtime Power Reduction. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Detailed placement for leakage reduction using systematic through-pitch variation. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
aCLV, through-pitch, leakage, lithography, detailed placement |
| 1 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester |
Line-End Shortening is Not Always a Failure. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman |
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng |
Design challenges at 65nm and beyond. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu |
Exploiting STI stress for performance. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu |
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sherief Reda |
Wirelength minimization for min-cut placements via placement feedback. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sherief Reda |
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu |
Wafer Topography-Aware Optical Proximity Correction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky |
Computer-Aided Optimization of DNA Array Design and Manufacturing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sherief Reda |
New and improved BIST diagnosis methods from combinatorial Group testing theory. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Gate-length biasing for runtime-leakage control. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng |
A Fast Hierarchical Quadratic Placement Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bao Liu, Xu Xu |
Constructing Current-Based Gate Models Based on Existing Timing Library. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Kambiz Samadi, Puneet Sharma |
Study of Floating Fill Impact on Interconnect Capacitance. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Impact of Gate-Length Biasing on Threshold-Voltage Selection. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan |
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bao Liu, Xu Xu |
Statistical gate delay calculation with crosstalk alignment consideration. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Qinke Wang |
A faster implementation of APlace. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
lens aberration, supply voltage degradation, scalability, analytical placement |
| 1 | Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan |
Efficient decoupling capacitor planning via convex programming methods. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bao Liu, Xu Xu |
Statistical crosstalk aggressor alignment aware interconnect delay calculation. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Rasit Onur Topaloglu |
Generation of design guarantees for interconnect matching. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
design guarantee generation, interconnect matching |
| 1 | Andrew B. Kahng, Sherief Reda |
A tale of two nets: studies of wirelength progression in physical design. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
placer suboptimality, benchmarking, consistency, similarity, wirelength |
| 1 | Andrew B. Kahng |
CAD challenges for leading-edge multimedia designs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saumil Shah, Puneet Gupta, Andrew B. Kahng |
Standard cell library optimization for leakage reduction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
| 1 | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
Timing-driven Steiner trees are (practically) free. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
arborescence, timing-driven, rectilinear Steiner tree |
| 1 | Puneet Gupta, Andrew B. Kahng |
Efficient Design and Analysis of Robust Power Distribution Meshes. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang |
Lens aberration aware timing-driven placement. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky |
Fill for shallow trench isolation CMP. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rasit Onur Topaloglu, Andrew B. Kahng |
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Puneet Gupta, Andrew B. Kahng, Stefanus Mantik |
Routing-aware scan chain ordering. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
testing, Layout, scan chain |
| 1 | Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma |
Layout-aware scan chain synthesis for improved path delay fault coverage. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng |
Compressible area fill synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Qinke Wang |
Implementation and extensibility of an analytic placer. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
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