Search results for "Andrew DeOrio"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen	A Reliable Routing Architecture and Algorithm for NoCs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Gate-Level Simulation with GPU Computing.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco	ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment.	PACT	2011	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh	DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips.	DAC	2011	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco	Post-silicon bug diagnosis with inconsistent executions.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco	Functional correctness for CMP interconnects.	ICCD	2011	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Valeria Bertacco	Electronic design automation for social networks.	DAC	2010	DBLP DOI BibTeX RDF	EDA algorithms, verification, social networks
1	Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen	Inferno: Streamlining Verification With Inferred Semantics.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Valeria Bertacco	Human computing for EDA.	DAC	2009	DBLP DOI BibTeX RDF	satisfiability, human computing
1	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
1	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Event-driven gate-level simulation with GP-GPUs.	DAC	2009	DBLP DOI BibTeX RDF	gate-level simulation, general purpose graphics processing unit (GP-GPU), high-performance simulation
1	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	GCS: High-performance gate-level simulation with GPGPUs.	DATE	2009	DBLP BibTeX RDF
1	David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw	A highly resilient routing algorithm for fault-tolerant NoCs.	DATE	2009	DBLP BibTeX RDF
1	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Post-silicon verification for cache coherence.	ICCD	2008	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Chico: An On-chip Hardware Checker for Pipeline Control Logic.	MTV	2007	DBLP DOI BibTeX RDF

Publications of "Andrew DeOrio" ( http://dblp.L3S.de/Authors/Andrew_DeOrio )