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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3 occurrences of 3 keywords
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Results
Found 15 publication records. Showing 15 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Vaibhav Madhok, Animesh Datta |
Interpreting quantum discord through quantum state merging  |
CoRR  |
2010 |
DBLP BibTeX RDF |
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| 1 | Martin Saint-Laurent, Animesh Datta |
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
clock gater, clock gating cell, local clock buffer, set-reset latch |
| 1 | Shrutilipi Bhattacharjee, Imon Banerjee, Animesh Datta |
An Ontology Based Framework for Domain Analysis of Interactive System. |
IC3 |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Imon Banerjee, Shrutilipi Bhattacharjee, Ranjan Dasgupta, Swapan Bhattacharya |
Framework for Domain Analysis of Teleteaching System: A Semiformal Approach. |
Software Engineering Research and Practice |
2010 |
DBLP BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
Profit Aware Circuit Design Under Process Variations Considering Speed Binning. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy |
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies |
CoRR |
2007 |
DBLP BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
Speed binning aware design methodology to improve profit under parameter variations. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy |
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
Asynchronous/synchronous operations, fault tolerance, energy-aware systems, algorithms implemented in hardware |
| 1 | Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy |
A process-tolerant cache architecture for improved yield in nanoscale technologies. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy |
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
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