Search results for "Ann Gordon-Ross"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Arslan Munir, Sanjay Ranka, Ann Gordon-Ross	High-Performance Energy-Efficient Multicore Embedded Computing.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross	An MDP-Based Dynamic Optimization Methodology for Wireless Sensor Networks.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Wei Zang, Ann Gordon-Ross	A single-pass cache simulation methodology for two-level unified caches.	ISPASS	2012	DBLP DOI BibTeX RDF
1	Marisha Rawlins, Ann Gordon-Ross	An application classification guided cache tuning heuristic for multi-core architectures.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky	Online algorithms for wireless sensor networks dynamic optimization.	CCNC	2012	DBLP DOI BibTeX RDF
1	Saleh Abdel-Hafeez, Ann Gordon-Ross	A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Abelardo Jara-Berrocal, Ann Gordon-Ross	Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources.	FPT	2011	DBLP DOI BibTeX RDF
1	Shaon Yousuf, Adam Jacobs, Ann Gordon-Ross	Partially reconfigurable system-on-chips for adaptive fault tolerance.	FPT	2011	DBLP DOI BibTeX RDF
1	Rohit Kumar, Ann Gordon-Ross	Formulation-level design space exploration for partially reconfigurable FPGAs.	FPT	2011	DBLP DOI BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross	Markov Modeling of Fault-Tolerant Wireless Sensor Networks.	ICCCN	2011	DBLP DOI BibTeX RDF
1	Abelardo Jara-Berrocal, Ann Gordon-Ross	An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips.	ASAP	2011	DBLP DOI BibTeX RDF
1	Wei Zang, Ann Gordon-Ross	T-SPaCS - A two-level single-pass cache simulation methodology.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Marisha Rawlins, Ann Gordon-Ross	On the interplay of loop caching, code compression, and cache configuration.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Marisha Rawlins, Ann Gordon-Ross	CPACT - The conditional parameter adjustment cache tuner for dual-core architectures.	ICCD	2011	DBLP DOI BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross, Sanjay Ranka	A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems.	ICCD	2011	DBLP DOI BibTeX RDF
1	Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross	Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks.	Embedded Systems Letters	2010	DBLP DOI BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross	SIP-Based IMS Signaling Analysis for WiMax-3G Interworking Architectures.	IEEE Trans. Mob. Comput.	2010	DBLP DOI BibTeX RDF	session initiation protocol (SIP), network architecture, IP multimedia subsystem (IMS)
1	Shaon Yousuf, Ann Gordon-Ross	DAPR: Design Automation for Partially Reconfigurable FPGAs.	ERSA	2010	DBLP BibTeX RDF
1	Ann Gordon-Ross, Abelardo Jara-Berrocal	VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems.	ERSA	2010	DBLP BibTeX RDF
1	Marisha Rawlins, Ann Gordon-Ross	Lightweight runtime control flow analysis for adaptive loop caching.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	embedded systems, low energy, architecture tuning, loop cache
1	Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross	Transaction-Level Modeling for Sensor Networks Using SystemC.	SUTC/UMC	2010	DBLP DOI BibTeX RDF	SystemC profiling, simulation, Sensor networks, transaction-level modeling
1	Abelardo Jara-Berrocal, Ann Gordon-Ross	VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems.	DATE	2010	DBLP BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky	A lightweight dynamic optimization methodology for wireless sensor networks.	WiMob	2010	DBLP DOI BibTeX RDF
1	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Fast Configurable-Cache Tuning With a Unified Second-Level Cache.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Rohit Kumar, Ann Gordon-Ross	Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs.	FPL	2009	DBLP DOI BibTeX RDF
1	Rafael Garcia, Ann Gordon-Ross, Alan D. George	Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks.	FCCM	2009	DBLP DOI BibTeX RDF	virtual architecture, FPGA, reconfigurable computing, Kalman filter, partial reconfiguration
1	Weixun Wang, Prabhat Mishra, Ann Gordon-Ross	SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Adam Flynn, Ann Gordon-Ross, Alan D. George	Bitstream relocation with local clock domains for partially reconfigurable FPGAs.	DATE	2009	DBLP BibTeX RDF
1	Abelardo Jara-Berrocal, Ann Gordon-Ross	SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems.	DATE	2009	DBLP BibTeX RDF
1	Abelardo Jara-Berrocal, Ann Gordon-Ross	Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time.	ReConFig	2009	DBLP DOI BibTeX RDF	field programmable gate arrays, partial reconfiguration, temporal partitioning, module placement
1	Arslan Munir, Ann Gordon-Ross	SIP-Based IMS Registration Analysis for WiMax-3G Interworking Architectures.	ICNS	2009	DBLP DOI BibTeX RDF
1	Arslan Munir, Ann Gordon-Ross	An MDP-based application oriented optimal policy for wireless sensor networks.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	wireless sensor networks, dynamic optimization, MDP
1	Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan D. George	Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Chris Conger, Ann Gordon-Ross, Alan D. George	Design Framework for Partial Run-Time FPGA Reconfiguration.	ERSA	2008	DBLP BibTeX RDF
1	Ann Gordon-Ross, Jeremy Lau, Brad Calder	Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	cache tuning, phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable caches, configurable architecture
1	Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid	A table-based method for single-pass cache optimization.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
1	Baoke Zhang, Karthik Sabhanatarajan, Ann Gordon-Ross, Alan D. George	Real-time performance analysis of Adaptive Link Rate.	LCN	2008	DBLP DOI BibTeX RDF
1	Karthik Sabhanatarajan, Ann Gordon-Ross	A resource efficient content inspection system for next generation Smart NICs.	ICCD	2008	DBLP DOI BibTeX RDF
1	Ann Gordon-Ross, Frank Vahid	A Self-Tuning Configurable Cache.	DAC	2007	DBLP DOI BibTeX RDF
1	Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros	A one-shot configurable-cache tuner for improved energy and performance.	DATE	2007	DBLP DOI BibTeX RDF
1	Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid	Configurable cache subsetting for fast cache tuning.	DAC	2006	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
1	Ann Gordon-Ross, Frank Vahid	Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Frequent value profiling, runtime profiling, on-chip profiling, hardware profiling, frequent loop detection, hot spot detection, dynamic optimization
1	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Fast configurable-cache tuning with a unified second-level cache.	ISLPED	2005	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache
1	Ann Gordon-Ross, Frank Vahid, Nikil Dutt	A first look at the interplay of code reordering and configurable caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cache exploration, code reorganization, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache, code layout, code reordering
1	Ann Gordon-Ross, Frank Vahid, Nikil Dutt	Automatic Tuning of Two-Level Caches to Embedded Applications.	DATE	2004	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, Configurable cache
1	Ann Gordon-Ross, Susan Cotterell, Frank Vahid	Tiny instruction caches for low power embedded systems.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	embedded systems., fixed program, low power, instruction cache, low energy, architecture tuning, Loop cache, filter cache
1	Ann Gordon-Ross, Frank Vahid	Frequent loop detection using efficient non-intrusive on-chip hardware.	CASES	2003	DBLP DOI BibTeX RDF	frequent loop detection, frequent value profiling, hardware profiling, hot spot detection, on-chip profiling, runtime profiling, dynamic optimization
1	Ann Gordon-Ross, Susan Cotterell, Frank Vahid	Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example.	Computer Architecture Letters	2002	DBLP DOI BibTeX RDF	fixed program, embedded systems, low power, architecture tuning, Loop cache
1	Ann Gordon-Ross, Frank Vahid	Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach.	ICCD	2002	DBLP DOI BibTeX RDF	embedded systems, architecture, low power, Loop cache
1	Frank Vahid, Ann Gordon-Ross	A self-optimizing embedded microprocessor using a loop table for low power.	ISLPED	2001	DBLP DOI BibTeX RDF	parameterized architectures, self-optimizing architecture, embedded systems, low-power, system-on-a-chip, platforms, cores, tuning

Publications of "Ann Gordon-Ross" ( http://dblp.L3S.de/Authors/Ann_Gordon-Ross )