| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda |
A SysML Profile for Development and Early Validation of TLM 2.0 Models.  |
ECMFA  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda |
A UML based framework for efficient validation of TLM 2 models. |
FDL |
2011 |
DBLP BibTeX RDF |
|
| 1 | Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar |
Exploiting temporal decoupling to accelerate trace-driven NoC emulation. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul |
A high-level synthesis flow for custom instruction set extensions for application-specific processors. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar |
Instruction Selection in ASIP Synthesis Using Functional Matching. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Functional Matching, ASIP, Covering, Confluence, Structural Matching |
| 1 | Anshul Kumar, Preeti Ranjan Panda |
Front-End Design Flows for Systems on Chip: An Embedded Tutorial. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
SoC Platform, Simulation, Prototyping, ASIPs, Design flow, Communication Architecture |
| 1 | Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar |
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. |
CODES+ISSS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Awadhesh Kumar Singh, Rohit Bhat, Anshul Kumar |
An Index-Based Mobile Checkpointing and Recovery Algorithm. |
ICDCN |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
International Journal of Parallel Programming |
2007 |
DBLP DOI BibTeX RDF |
Performance evaluation, VLIW, ASIP, Clustered VLIW processors |
| 1 | Anup Gangwar, M. Balakrishnan, Anshul Kumar |
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
performance evaluation, VLIW, ASIP, clustered VLIW processors |
| 1 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Recurring Pattern Identification and its Application to Instruction Set Extension. |
CDES |
2007 |
DBLP BibTeX RDF |
|
| 1 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Application Specific Datapath Extension with Distributed I/O Functional Units. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar |
Rapid Resource-Constrained Hardware Performance Estimation. |
IEEE International Workshop on Rapid System Prototyping |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
Integrated On-Chip Storage Evaluation in ASIP Synthesis. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet |
Battery Model for Embedded Systems. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne |
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. |
SCOPES |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourabh Saluja, Anshul Kumar |
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan |
Synthesis of Application Specific Multiprocessor Architectures for Process Networks. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkat Rao, Gaurav Singhal, Anshul Kumar |
Real Time Dynamic Voltage Scaling For Embedded Systems. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan |
Automatic synthesis of system on chip multiprocessor architectures for process networks. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
application specific multiprocessors, partitioning, Kahn process networks |
| 1 | Sushil Chandra Jain, Anshul Kumar, Shashi Kumar |
Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing. |
Design Autom. for Emb. Sys. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
Exploring Storage Organization in ASIP Synthesis. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar |
SoC Synthesis with Automatic Hardware Software Interface Generation. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar |
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sushil Chandra Jain, Anshul Kumar, Shashi Kumar |
Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. |
IEEE International Workshop on Rapid System Prototyping |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP synthesis. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis |
| 1 | M. Balakrishnan, Anshul Kumar, C. P. Joshi |
A New Performance Evaluation Approach for System Level Design Space Exploration. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
design space exploration, system level design, statistical simulation |
| 1 | M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha |
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
Trimaran, performance, design space exploration, VLIW, ASIP |
| 1 | Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar |
Exploring the Number of Register Windows in ASIP Synthesis. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows |
| 1 | Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan |
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT |
| 1 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
ASIP Design Methodologies : Survey and Issues. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Anupam Rastogi, M. Balakrishnan, Anshul Kumar |
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa |
Synthesizing A Long Latency Unit Within Vliw Processor. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A scheme for multiple on-chip signature checking for embedded SRAMS. |
Journal of Systems Architecture |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Johnny Öberg, Anshul Kumar, Ahmed Hemani |
Grammar-based hardware synthesis from port-size independent specifications. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sushil Chandra Jain, Anshul Kumar, Shashi Kumar |
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Arvind Rajawat, M. Balakrishnan, Anshul Kumar |
nterface Synthesis: Issues and Approaches. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Codesign methodology, Interface optimization, Communication protocols, Interface synthesis |
| 1 | Sushil Chandra Jain, Shashi Kumar, Anshul Kumar |
Evaluation of Various Routing Architectures for Multi-FPGA Boards. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable Computing, Rapid Prototyping |
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Built-in Self Test Based on Multiple On-Chip Signature Checking. |
J. Electronic Testing |
1999 |
DBLP DOI BibTeX RDF |
multiple signature comparison testing, BIST, aliasing probability |
| 1 | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
Direct mapping of RTL structures onto LUT-based FPGA's. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. |
J. Electronic Testing |
1998 |
DBLP DOI BibTeX RDF |
mutual checking, multiple signature testing, self loops, built-in self test, aliasing |
| 1 | Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar |
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | Johnny Öberg, Axel Jantsch, Anshul Kumar |
An Object-Oriented Concept for Intelligent Library Functions. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Core Based Design Methodology, Intelligent Library Functions, Object-Oriented |
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Hybrid Testing Schemes Based on Mutual and Signature Testing. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
On-Chip Signature Checking for Embedded Memories. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | Johnny Öberg, Ahmed Hemani, Anshul Kumar |
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Johnny Öberg, Anshul Kumar, Ahmed Hemani |
Specification of Exception Handling in Grammar-Based Hardware Synthesis. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Efficient Implementation of Multiple On-Chip Signature Checking. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
Optimal Clock Period for Synthesized Data Paths. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A scheme for multiple on-chip signature checking for embedded SRAMs. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Johnny Öberg, Anshul Kumar, Ahmed Hemani |
Grammar-Based Hardware Synthesis of Data Communication Protocols. (PDF / PS) |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
Grammar-based Specification, Data Communication Protocols, Design Space Exploration, Hardware Synthesis |
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A Novel BIST Architecture With Built-in Self Check. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. |
FPL |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Alok Kumar, Anshul Kumar, M. Balakrishnan |
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs |
| 1 | B. M. Subraya, Anshul Kumar, Shashi Kumar |
An HOL based framework for design of correct high level synthesizers. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
HOL based framework, high level synthesizer design, design correctness guarantee, verifiable templates, synthesis module correctness, formal verification, high level synthesis, modularity, formal logic, higher order logic, verification process, formal framework |
| 1 | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
An Efficient Technique for Mapping RTL Structures onto FPGAs. |
FPL |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
FAST: FPGA Targeted RTL Structure Synthesis Technique. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
|
| 1 | M. V. Rao, M. Balakrishnan, Anshul Kumar |
DESSERT: Design Space Exploration of RT Level Components. |
VLSI Design |
1993 |
DBLP BibTeX RDF |
|
| 1 | C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer |
High Level Design Experiences with IDEAS. |
VLSI Design |
1993 |
DBLP BibTeX RDF |
|
| 1 | Anjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra |
Automatic generation of digital system schematic diagrams. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar Ramayya, Anshul Kumar, Surendra Prasad |
An automated data path synthesizer for a canonic structure, implementable in VLSI. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
| 1 | Anshul Kumar, P. C. P. Bhatt |
A Structured Language for CAD of Digital Systems. |
ISCA |
1980 |
DBLP DOI BibTeX RDF |
|
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