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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 10 keywords
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Results
Found 21 publication records. Showing 21 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Antonio G. M. Strollo, Davide De Caro, Nicola Petra |
Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations.  |
IEEE Trans. Computers  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo |
Design of Fixed-Width Multipliers With Linear Compensation Function. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
Efficient Logarithmic Converters for Digital Signal Processing Applications. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio G. M. Strollo, Claudio Parrella |
A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. |
J. Solid-State Circuits |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo |
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Valeria Garofalo, Marino Coppola, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo |
A novel truncated squarer with linear compensation function. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Marino Coppola, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo, Valeria Garofalo |
High-speed differential resistor ladder for A/D converters. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Valeria Garofalo, Ettore Napoli, Marino Coppola, Pietro Todisco |
Fixed-width CSD multipliers with minimum mean square error. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
High-Performance Special Function Unit for Programmable 3-D Graphics Processors. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Paolo Pulici, Antonio Girardi, Gianpietro P. Vanalli, Roberto Izzi, Giacomo Bernardi, Giancarlo Ripamonti, Antonio G. M. Strollo, Giovanni Campardo |
A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Nicola Petra, Antonio G. M. Strollo |
A high performance floating-point special function unit using constrained piecewise quadratic approximation. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Nicola Petra, Davide De Caro, Antonio G. M. Strollo |
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
VLSI, High-Performance, Digital, Reed-Solomon codes, Arithmetic, finite field multiplication, polynomial basis |
| 1 | Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra |
A novel high-speed sense-amplifier-based flip-flop. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio G. M. Strollo, Davide De Caro |
Direct digital frequency synthesizers exploiting piecewise linear Chebyshev approximation. |
Microelectronics Journal |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo |
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo |
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio G. M. Strollo, Ettore Napoli, C. Cimino |
Analysis of power dissipation in double edge-triggered flip-flops. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio G. M. Strollo, Ettore Napoli, Davide De Caro |
New clock-gating techniques for low-power flip-flops. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits |
Displaying result #1 - #21 of 21 (100 per page; Change: )
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