Search results for "Antonio Pullini"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal	Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
1	Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini	Networks on Chips: from research to products.	DAC	2010	DBLP DOI BibTeX RDF	SoC, system on chip, network on chip, NoC
1	Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini	3D NoCs - Unifying inter & intra chip communication.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli	Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.	DATE	2009	DBLP BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii	Physically clustered forward body biasing for variability compensation in nanometer CMOS design.	DATE	2009	DBLP BibTeX RDF
1	Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini	A floorplan-aware interactive tool flow for NoC design and synthesis.	SoCC	2009	DBLP DOI BibTeX RDF
1	David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli	Network-on-Chip design and synthesis outlook.	Integration	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	A Scalable Algorithmic Framework for Row-Based Power-Gating.	DATE	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini	Bringing NoCs to 65 nm.	IEEE Micro	2007	DBLP DOI BibTeX RDF	network on chip, low-power design, power management, multicore architectures, on-chip interconnection networks, design aids, deep submicron design
1	Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli	Timing-Error-Tolerant Network-on-Chip Design Methodology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini	NoC Design and Implementation in 65nm Technology.	NOCS	2007	DBLP DOI BibTeX RDF
1	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
1	Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini	Fault tolerance overhead in network-on-chip flow control schemes.	SBCCI	2005	DBLP DOI BibTeX RDF	fault tolerance, network on chip, error correction, flow control

Publications of "Antonio Pullini" ( http://dblp.L3S.de/Authors/Antonio_Pullini )