Search results for "Antonis M. Paschalis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	Low Energy Online Self-Test of Embedded Processors in Dependable WSN Nodes.	IEEE Trans. Dependable Sec. Comput.	2012	DBLP DOI BibTeX RDF
1	Antonis M. Paschalis, Ioannis Voyiatzis, Dimitris Gizopoulos	Accumulator Based 3-Weight Pattern Generation.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	A Software-Based Self-Test methodology for on-line testing of processor caches.	ITC	2011	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	Recursive Pseudo-Exhaustive Two-Pattern Generation.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Andreas Merentitis, D. Margaris, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	SBST for on-line detection of hard faults in multiprocessor applications under energy constraints.	IOLTS	2010	DBLP DOI BibTeX RDF
1	George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	A software-based self-test methodology for in-system testing of processor cache tag arrays.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Andreas Merentitis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis	Energy optimal on-line Self-Test of microprocessors in WSN nodes.	ICCD	2010	DBLP DOI BibTeX RDF
1	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar	Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors.	European Test Symposium	2009	DBLP DOI BibTeX RDF	Chip multithreading, micro-processor testing, functional self-testing, test time optimization, multiprocessors, software-based self-testing
1	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	An Input Vector Monitoring Concurrent BIST scheme exploiting .	IOLTS	2009	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail	An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi	Systematic Software-Based Self-Test for Pipelined Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos	Hybrid-SBST Methodology for Efficient Testing of Processor Cores.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test
1	Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	Low Energy On-Line SBST of Embedded Processors.	ITC	2008	DBLP DOI BibTeX RDF
1	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
1	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Miltiadis Hatzimihail, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	A methodology for detecting performance faults in microprocessors via performance monitoring hardware.	ITC	2007	DBLP DOI BibTeX RDF
1	Andreas Merentitis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	Selecting Power-Optimal SBST Routines for On-Line Processor Testing.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors.	DFT	2007	DBLP DOI BibTeX RDF
1	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs.	IOLTS	2007	DBLP DOI BibTeX RDF
1	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
1	Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi	Systematic software-based self-test for pipelined processors.	DAC	2006	DBLP DOI BibTeX RDF	functional testing, software-based self-test, processor testing
1	Nektarios Kranitis, Andreas Merentitis, N. Laoutaris, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis	Optimal periodic testing of intermittent faults in embedded pipelined processor applications.	DATE	2006	DBLP DOI BibTeX RDF
1	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis	A concurrent built-in self-test architecture based on a self-testing RAM.	IEEE Transactions on Reliability	2005	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis	Software-Based Self-Testing of Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor self-testing, Embedded processors, software-based self-testing, low-cost testing
1	Antonis M. Paschalis, Dimitris Gizopoulos	Effective software-based self-test strategies for on-line periodic testing of embedded processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis, Constantin Halatsis	A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set.	ITC	2005	DBLP DOI BibTeX RDF
1	Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis	Software-Based Self-Test for Pipelined Processors: A Case Study.	DFT	2005	DBLP DOI BibTeX RDF
1	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation Methodology for High-Speed Floating Point Adders.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	Accumulator-Based Weighted Pattern Generation.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Antonis M. Paschalis, Dimitris Gizopoulos	Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors.	DATE	2004	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	processor cores, built-in self-test, instruction set, at-speed testing, software-based self test
1	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Easily Testable Cellular Carry Lookahead Adders.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
1	Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.	ITC	2003	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Low-Cost Software-Based Self-Testing of RISC Processor Cores.	DATE	2003	DBLP DOI BibTeX RDF
1	George Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis	Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores.	IOLTS	2003	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	VTS	2002	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Effective Software Self-Test Methodology for Processor Cores.	DATE	2002	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	datapath test, shifter, Built-in self-test, accumulator, arithmetic-logic unit, processor test
1	Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.	ISQED	2001	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
1	Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian	Deterministic software-based self-testing of embedded processor cores.	DATE	2001	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
1	Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian	Power-/Energy Efficient BIST Schemes for Processor Data Paths.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Low Power/Energy BIST Scheme for Datapaths.	VTS	2000	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Effective Low Power BIST for Datapaths.	DATE	2000	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Built-In Self-Test Scheme for Parallel Multipliers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	tree multipliers, Built-in self-test, array multipliers, cell fault model
1	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An Accumulator-Based BIST Approach for Two-Pattern Testing.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	stuck-open fault testing, built-in self test, delay fault testing, two-pattern testing
1	Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers.	VTS	1999	DBLP DOI BibTeX RDF
1	Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Fast Multiplier Cores.	DATE	1999	DBLP DOI BibTeX RDF
1	Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis	Concurrent Delay Testing in Totally Self-Checking Systems.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators
1	Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis	A Totally Self-Checking 1-out-of-3 Code Error Indicator.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	1-out-of-3 code, totally self checking circuits, error indicator
1	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model
1	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Design & Test of Computers	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
1	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis	R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique.	ITC	1998	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis	An Effective BIST Scheme for Arithmetic Logic Units.	ITC	1997	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
1	Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis	A totally self-checking 1-out-of-3 code error indicator.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An efficient built-in self test method for robust path delay fault testing.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test
1	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
1	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing CMOS combinational iterative logic arrays for realistic faults.	Integration	1996	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective BIST Scheme for Datapaths.	ITC	1996	DBLP DOI BibTeX RDF
1	Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis	An asynchronous totally self-checking two-rail code error indicator.	VTS	1996	DBLP DOI BibTeX RDF	asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults
1	Vassilios V. Dimakopoulos, G. Sourtziotis, Antonis M. Paschalis, Dimitris Nikolos	On TSC Checkers for m-out-n Codes.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	MOS transistor implementation, fault tolerance, Fault detection, totally self-checking checkers, m-out-of-n code
1	Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos	Efficient Totally Self-Checking Checkers for a Class of Borden Codes.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Borden codes, t-unidirectional error detecting (t-UED) codes, fault tolerant, fault detection, totally self-checking checker
1	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective BIST Scheme for Booth Multipliers.	ITC	1995	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An effective BIST scheme for carry-save and carry-propagate array multipliers.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
1	Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis	Totally Self Checking reconfigurable duplication system with separate internal fault indication.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	decision circuits, totally self checking system, reconfigurable duplication system, separate internal fault indication, single cell fault model, functional self checking units, decision circuit, indication outputs, nonstop repair, fault diagnosis, logic testing, built-in self test, redundancy, redundancy, reconfigurable architectures, switching circuits, error indication
1	Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis	An efficient comparative concurrent Built-In Self-Test technique.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	off-line test generation, comparative concurrent BIST, test latency, windowed-CBIST, VLSI, logic testing, built-in self test, integrated circuit testing, concurrent engineering, VLSI circuits, test sequence, hardware overhead
1	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
1	Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis	An Efficient TSC 1-out-of-3 Code Checker.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	TSC 1-out-of-3 code checker, combinational totally self-checking, logic testing, logic design, automatic testing, integrated logic circuits
1	Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	half-adder, VLSI MOS implementation, logic design, trees, codes, codes, adders, modular design, totally self-checking checkers, full-adder
1	Dimitris Nikolos, Antonis M. Paschalis, George Philokyprou	Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	low-cost arithmetic codes, reliability, fault tolerant computing, partitioning, trees, error detection codes, totally self-checking checkers, gate levels
1	Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.	Aegean Workshop on Computing	1986	DBLP DOI BibTeX RDF

Publications of "Antonis M. Paschalis" ( http://dblp.L3S.de/Authors/Antonis_M._Paschalis )