Search results for "Antonis Papanikolaou"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Nikolaos Zompakis, Antonis Papanikolaou, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor	Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.	SiPS	2011	DBLP DOI BibTeX RDF
1	Kostas Siozios, Antonis Papanikolaou, Dimitrios Soudris	CAD tools for designing 3D integrated systems.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Filippos Toufexis, Antonis Papanikolaou, Dimitrios Soudris, George I. Stamoulis, Sotiris Bantas	Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm.	ICECS	2011	DBLP DOI BibTeX RDF
1	Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Wilfried Philips	Control for Power Gating of Wires.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi	A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Alienor Richard, Dragomir Milojevic, Frédéric Robert, Alexandros Bartzas, Antonis Papanikolaou, Kostas Siozios, Dimitrios Soudris	Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's.	ARCS Workshops	2010	DBLP BibTeX RDF
1	Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris	BIT-width exploration over 3D architectures using high-level synthesis.	ICECS	2010	DBLP DOI BibTeX RDF
1	Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor	System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	Combining system scenarios and configurable memories to tolerate unpredictability.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	variability compensation, Process variation, parametric yield
1	Jin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor	A tool flow for predicting system level timing failures due to interconnect reliability degradation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	system degradation, system level failures, interconnect reliability
1	Jin Guo, Antonis Papanikolaou, H. Zhang, Francky Catthoor	Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Jin Guo, Antonis Papanikolaou, Francky Catthoor	Topology exploration for energy efficient intra-tile communication.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Concepción Sanz, Manuel Prieto, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	System-level process variability compensation on memory organizations of dynamic applications: a case study.	ISQED	2006	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei	Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor	Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.	SLIP	2006	DBLP DOI BibTeX RDF	segmented bus, floorplanning, trade-offs
1	Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor	Physical design implementation of segmented buses to reduce communication energy.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips	Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture.	ARC	2006	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, T. Grabner, Miguel Miranda, Philippe Roussel, Francky Catthoor	Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system exploration, process variability, parametric yield
1	Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene	Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor	A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	system-level compensation, process variability, parametric yield
1	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	combined system design and process technology exploration, optimal energy/delay trade-off exploration in memories
1	Hua Wang, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Global interconnect trade-off for technology over memory modules to application level: case study.	SLIP	2003	DBLP DOI BibTeX RDF	Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
1	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Interconnect exploration for future wire dominated technologies.	SLIP	2002	DBLP DOI BibTeX RDF	interconnect wire processing, intra/inter-memory interconnect, pareto-optimal energy/delay interconnect exploration

Publications of "Antonis Papanikolaou" ( http://dblp.L3S.de/Authors/Antonis_Papanikolaou )