Search results for "Arijit Raychowdhury"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky	Design for test and reliability in ultimate CMOS.	DATE	2012	DBLP BibTeX RDF
1	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Minki Cho, Nikhil Sathe, Arijit Raychowdhury, Saibal Mukhopadhyay	Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration.	ITC	2010	DBLP DOI BibTeX RDF
1	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Resilient microprocessor design for high performance & energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	resilient design
1	Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.	CICC	2010	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.	ISSCC	2010	DBLP DOI BibTeX RDF
1	James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.	ISSCC	2010	DBLP DOI BibTeX RDF
1	James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De	Resilient design in scaled CMOS for energy efficiency.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy	PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.	ISQED	2009	DBLP DOI BibTeX RDF
1	Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath	A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
1	Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim	Leakage Power Analysis and Reduction for Nanoscale Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	nanoscale circuits, CMOS, technology scaling, leakage power reduction
1	Arijit Raychowdhury, Kaushik Roy	Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy	Analysis of super cut-off transistors for ultralow power digital logic circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	carbon nanotube FETs, tunneling transistors
1	Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy	A high density, carbon nanotube capacitor for decoupling applications.	DAC	2006	DBLP DOI BibTeX RDF	interconnect, carbon nanotube, three-dimensional, capacitor
1	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.	IOLTS	2006	DBLP DOI BibTeX RDF	Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion
1	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy	Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	Defect Oriented Testing (DOT), dynamic supply current (IDD), wavelet transform, Fourier transform
1	Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	analog filter, trim bit, dynamic supply current (IDD), wavelet transform, frequency response
1	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.	IOLTS	2005	DBLP DOI BibTeX RDF	Speed binning, delay measurement hardware, process variation
1	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy	A Feasibility Study of Subthreshold SRAM Across Technology Generations.	ICCD	2005	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	ICCD	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy	A circuit-compatible model of ballistic carbon nanotube field-effect transistors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.	ISQED	2004	DBLP DOI BibTeX RDF	Analog Filer, Trim Bit, Dynamic Supply Current (IDD), Wavelet Transform
1	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy	Device optimization for ultra-low power digital sub-threshold operation.	ISLPED	2004	DBLP DOI BibTeX RDF	device optimization, sub-threshold operation, ultra-low power applications
1	Arijit Raychowdhury, Kaushik Roy	A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.	ISMVL	2004	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy	Modeling and Estimation of Leakage in Sub-90nm Devices.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.	DATE	2004	DBLP DOI BibTeX RDF	Analog Filer, Trim Bit, Dynamic Supply Current (IDD), Wavelet Transform
1	Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy	Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Kaushik Roy	A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
1	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy	Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.	ICCAD	2003	DBLP DOI BibTeX RDF	SPICE

Publications of "Arijit Raychowdhury" ( http://dblp.L3S.de/Authors/Arijit_Raychowdhury )