Search results for "Aristides Efthymiou"

Found 17 publication records. Showing 17 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Aristides Efthymiou	Initialization-Based Test Pattern Generation for Asynchronous Circuits.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume	Optimising Self-Timed FPGA Circuits.	DSD	2010	DBLP DOI BibTeX RDF
1	Dilip P. Vasudevan, Aristides Efthymiou	A Partial Scan Based Test Generation for Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
1	Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou	Synthetic Trace-Driven Simulation of Cache Memory.	AINA Workshops	2007	DBLP DOI BibTeX RDF
1	Aristides Efthymiou	Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.	DDECS	2007	DBLP BibTeX RDF
1	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
1	Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou	Fast, Parallel Two-Rail Code Checker with Enhanced Testability.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	A CAM with mixed serial-parallel comparison for use in low energy caches.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Adding Testability to an Asynchronous Interconnect for GALS SoC.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury	An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Structures fo Speculation Control.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Aristides Efthymiou, Jim D. Garside	An adaptive serial-parallel CAM architecture for low-power cache blocks.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low power, asynchronous circuits, low energy, CAM, cache design
1	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Depth Control for Processor Power-Management.	ICCD	2002	DBLP DOI BibTeX RDF
1	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple	Power Management in the Amulet Microprocessors.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou	Pipelined Memory Shared Buffer for VLSI Switches.	SIGCOMM	1995	DBLP DOI BibTeX RDF	gigabit VLSI switch buffer, multiport buffer, pipelined memory, crossbar switch, shared buffering, input queueing

Publications of "Aristides Efthymiou" ( http://dblp.L3S.de/Authors/Aristides_Efthymiou )