Search results for "Arnaldo Azevedo"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero	A Highly Scalable Parallel Implementation of H.264.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Ben H. H. Juurlink	An Instruction to Accelerate Software Caches.	ARCS	2011	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Ben H. H. Juurlink	A Multidimensional Software Cache for Scratchpad-Based Systems.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Alex Ramírez, Felipe Cabarcas, Ben H. H. Juurlink, Mauricio Alvarez, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Bogdan Ciobanu, Sebastian Isaza, Georgi Gaydadjiev	The SARC Architecture.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Mauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck	Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA.	RASI	2009	DBLP BibTeX RDF
1	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez	Parallel Scalability of Video Decoders.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
1	M. Alvarez Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero	Scalability of Macroblock-level Parallelism for H.264 Decoding.	ICPADS	2009	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez	Parallel H.264 Decoding on an Embedded Multicore Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Arnaldo P. Azevedo Filho, Ben H. H. Juurlink	Scalar Processing Overhead on SIMD-Only Architectures.	ASAP	2009	DBLP DOI BibTeX RDF
1	Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink	Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture.	DSD	2008	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez	Analysis of video filtering on the cell processor.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin	FPGA Prototyping Strategy for a H.264/AVC Video Decoder.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Luciano Volcan Agostini, Arnaldo P. Azevedo Filho, Wagston T. Staehler, Vagner S. Rosa, Bruno Zatt, Ana Cristina M. Pinto, Roger Endrigo Carvalho Porto, Sergio Bampi, Altamiro Amadeu Susin	Design and FPGA Prototyping of a H.264/AVC Main Profile.	J. Braz. Comp. Soc.	2007	DBLP DOI BibTeX RDF
1	Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin	FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.	FPL	2006	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi	Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo	When reconfigurable architecture meets network-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	multiprocessor, system on chip, network on chip, reconfigurable architecture
1	Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva	A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva	X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva	X4CP32: A New Parallel/Reconfigurable General-Purpose Processor.	SBAC-PAD	2003	DBLP DOI BibTeX RDF

Publications of Arnaldo Azevedo Arnaldo P. Azevedo Filho ( http://dblp.L3S.de/Authors/Arnaldo_Azevedo )