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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, David Atienza |
Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Alessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza |
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | David Atienza, Arvind Sridhar |
Tutorial T7A: New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future.  |
VLSI Design  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Mohamed M. Sabry, Arvind Sridhar, David Atienza |
Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation.  |
DATE  |
2012 |
DBLP BibTeX RDF |
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| 1 | Alessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza |
Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs.  |
ISLPED  |
2011 |
DBLP BibTeX RDF |
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| 1 | Mohamed M. Sabry, Arvind Sridhar, David Atienza, Yuksel Temiz, Yusuf Leblebici, S. Szczukiewicz, N. Borhani, J. R. Thome, Thomas Brunschwiler, Bruno Michel |
Towards thermally-aware design of 3D MPSoCs with inter-tier cooling.  |
DATE  |
2011 |
DBLP BibTeX RDF |
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| 1 | José L. Ayala, Arvind Sridhar, David Cuesta |
Thermal modeling and analysis of 3D multi-processor chips.  |
Integration  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, David Atienza |
3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling.  |
ICCAD  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici |
Through Silicon Via-Based Grid for Thermal Control in 3D Chips.  |
NanoNet  |
2009 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #9 of 9 (100 per page; Change: )
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