Search results for "Ashoka Visweswara Sathanur"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor	Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
1	Ashoka Visweswara Sathanur, Jos Huisken, Jan Stuyt, Harmke de Groot	Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs.	ICECS	2010	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii	Physically clustered forward body biasing for variability compensation in nanometer CMOS design.	DATE	2009	DBLP BibTeX RDF
1	Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal-Aware Design Techniques for Nanometer CMOS Circuits.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.	Integration	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	A Scalable Algorithmic Framework for Row-Based Power-Gating.	DATE	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
1	Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.	DATE	2007	DBLP DOI BibTeX RDF
1	Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino	Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF

Publications of "Ashoka Visweswara Sathanur" ( http://dblp.L3S.de/Authors/Ashoka_Visweswara_Sathanur )