Search results for "Ashutosh Chakraborty"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ashutosh Chakraborty, David Z. Pan	Controlling NBTI degradation during static burn-in testing.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli	CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Sean X. Shi, David Z. Pan	Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
1	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
1	Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli	Performance analysis of 3-D monolithic integrated circuits.	3DIC	2010	DBLP DOI BibTeX RDF
1	Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim	Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
1	Ashutosh Chakraborty, Anurag Kumar, David Z. Pan	RegPlace: a high quality open-source placement framework for structured ASICs.	DAC	2009	DBLP DOI BibTeX RDF	global placement, regular ASIC, FPGA, placement, legalization, structured ASIC
1	Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan	Analysis and optimization of NBTI induced clock skew in gated clock trees.	DATE	2009	DBLP BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.	Integration	2008	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan	An integrated nonlinear placement framework with congestion and porosity aware buffer planning.	DAC	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, buffer
1	Ashutosh Chakraborty, Sean X. Shi, David Z. Pan	Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
1	Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal resilient bounded-skew clock tree optimization methodology.	DATE	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Enrico Macii, Massimo Poncino	Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Pradeep Varma, Ashutosh Chakraborty	Low-Voltage, Double-Edge-Triggered Flip Flop.	PATMOS	2003	DBLP DOI BibTeX RDF

Publications of "Ashutosh Chakraborty" ( http://dblp.L3S.de/Authors/Ashutosh_Chakraborty )