Search results for "Asim J. Al-Khalili"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria	Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria	Activity management in battery-powered embedded systems: A case study of ZigBee® WSN.	ICECS	2011	DBLP DOI BibTeX RDF
1	Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria	Analysis of Resistive Open Defects in Drowsy SRAM Cells.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	Repeater insertion in power-managed VLSI systems.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan	Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan	Skew compensation in energy recovery clock distribution networks.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Ali M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili	Pattern-Driven Clock Tree Routing with Via Minimization.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	An interconnect-aware delay model for dynamic voltage scaling in NM technologies.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dynamic voltage scaling (dvs), interconnects, delay model
1	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	Estimation of energy performance in computing platforms.	ICECS	2009	DBLP DOI BibTeX RDF
1	A. J. Al-Khalili	A CAD Tool for Scalable, Variable Architecture Floating-Point Adder Generator.	AICCSA	2006	DBLP DOI BibTeX RDF
1	Asim J. Al-Khalili	A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
1	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili	Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili	Delay analysis of CMOS gates using modified logical effort model.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Shaoqiang Bi, Warren J. Gross, Wei Wang 0003, Asim J. Al-Khalili, M. N. S. Swamy	An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Shaoqiang Bi, Wei Wang 0003, Asim J. Al-Khalili	Modulo deflation in (2n+1, 2n, 2n-1) converters.	ISCAS	2004	DBLP BibTeX RDF
1	Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili	Technology-portable analytical model for DSM CMOS inverter transition-time estimation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch	Low-Power Constant-Coefficient Multiplier Generator.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	constant multipliers, low power, VHDL, DSP, design automation, integer multiplication
1	Asim J. Al-Khalili, Aiping Hu	Design of a 32-bit squarer - exploiting addition redundancy.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili	Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	VLSI, clock distribution network, zero skew
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
1	Adnan Kabbani, A. J. Al-Khalili	Dynamic CMOS noise immunity estimation in submicron regime.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Adnan Kabbani, A. J. Al-Khalili	Estimation of ground bounce effects on CMOS circuits.	ISCAS	1999	DBLP DOI BibTeX RDF
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	An IEEE Compliant Floating Point MAF.	VLSI	1999	DBLP BibTeX RDF
1	Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili	Lossy Compression of Images Using Logic Minimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	Power implications of precision limited arithmetic in floating point FIR filters.	ISCAS	1999	DBLP DOI BibTeX RDF
1	R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili	A Low Power Floating Point Accumulator.	VLSI Design	1998	DBLP DOI BibTeX RDF	low power CMOS, Digital arithmetic, VLSI architecture, floating point
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition.	ISLPED	1997	DBLP DOI BibTeX RDF
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	A Low Power Approach to Floating Point Adder Design.	ICCD	1997	DBLP BibTeX RDF
1	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili	Energy delay analysis of partial product reduction methods for parallel multiplier implementation.	ISLPED	1996	DBLP DOI BibTeX RDF	SPICE
1	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Area efficient computing structures for concurrent error detection in systolic arrays.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
1	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili	Design techniques for fault-tolerant systolic arrays.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
1	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Design Methodology for Fault-Tolerant Systolic Array Architectures.	ICPP	1992	DBLP BibTeX RDF
1	F. Rouatbi, Baher Haroun, Asim J. Al-Khalili	Power estimation tool for sub-micron CMOS VLSI circuits.	ICCAD	1992	DBLP DOI BibTeX RDF
1	R. V. Dantu, Nikitas J. Dimopoulos, R. V. Patel, A. J. Al-Khalili	Depth perception using blurring and its application in VLSI wafer probing.	Mach. Vis. Appl.	1991	DBLP DOI BibTeX RDF
1	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	On the Design of Optimal Fault-Tolerant Systolic Array Architecures.	IPPS	1991	DBLP BibTeX RDF
1	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures.	ICPP	1991	DBLP BibTeX RDF
1	Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili	A module generator for optimized CMOS buffers.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
1	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Design of optimal systolic arrays: a systematic approach.	SPDP	1990	DBLP DOI BibTeX RDF
1	Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili	A Module Generator for Optimized CMOS Buffers.	DAC	1989	DBLP DOI BibTeX RDF
1	Asim J. Al-Khalili	An Algorithm for an Intelligent Arabic Computer Terminal.	International Journal of Man-Machine Studies	1984	DBLP DOI BibTeX RDF
1	C. J. Macleod, Asim J. Al-Khalili	An On-Line Optimization Procedure for an Urban Traffic System.	Optimization Techniques	1973	DBLP DOI BibTeX RDF

Publications of Asim J. Al-Khalili A. J. Al-Khalili ( http://dblp.L3S.de/Authors/Asim_J._Al-Khalili )