Search results for "Asit K. Mishra"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das	RAFT: A router architecture with frequency tuning for on-chip networks.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	A case for heterogeneous on-chip interconnects for CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan	An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.	DAC	2011	DBLP DOI BibTeX RDF
1	Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das	ACCESS: Smart scheduling for asymmetric cache CMPs.	HPCA	2011	DBLP DOI BibTeX RDF
1	Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut T. Kandemir, Chita R. Das	METE: meeting end-to-end QoS in multicores through system-wide resource management.	SIGMETRICS	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Joseph L. Hellerstein, Walfredo Cirne, Chita R. Das	Towards characterizing cloud backend workloads: insights from Google compute clusters.	SIGMETRICS Performance Evaluation Review	2010	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors.	SC	2010	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	Coordinated power management of voltage islands in CMPs.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	chip multiprocessors (CMP), control theory, GALs, DVFs
1	Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir	A case for integrated processor-cache partitioning in chip multiprocessors.	SC	2009	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das	A case for dynamic frequency tuning in on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF
1	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	MIRA: A Multi-layered On-Chip Interconnect Router Architecture.	ISCA	2008	DBLP DOI BibTeX RDF
1	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das	Performance and power optimization through data compression in Network-on-Chip architectures.	HPCA	2008	DBLP DOI BibTeX RDF

Publications of "Asit K. Mishra" ( http://dblp.L3S.de/Authors/Asit_K._Mishra )