Search results for "Avinoam Kolodny"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	The complexity of VLSI power-delay optimization by interconnect resizing.	J. Comb. Optim.	2012	DBLP DOI BibTeX RDF
1	Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson	Exploring the limits of GPGPU scheduling in control flow bound applications.	TACO	2012	DBLP DOI BibTeX RDF
1	Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny	Multi-aggressor capacitive and inductive coupling noise modeling and mitigation.	Microelectronics Journal	2012	DBLP DOI BibTeX RDF
1	Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser	Task Scheduling Based On Thread Essence and Resource Limitations.	JCP	2012	DBLP DOI BibTeX RDF
1	Yoni Aizik, Avinoam Kolodny	Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez	Static timing analysis for modeling QoS in networks-on-chip.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny	NoCs simulation framework for OMNeT++.	NOCS	2011	DBLP BibTeX RDF
1	Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny	Delay analysis of wormhole based heterogeneous NoC.	NOCS	2011	DBLP BibTeX RDF
1	Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer	A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.	DSD	2011	DBLP DOI BibTeX RDF
1	Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny	An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman	Memristor-based IMPLY logic design procedure.	ICCD	2011	DBLP DOI BibTeX RDF
1	Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter	Centralized Adaptive Routing for NoCs.	Computer Architecture Letters	2010	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect Bundle Sizing Under Discrete Design Rules.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar	Asynchronous Current Mode Serial Communication.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
1	Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny	The Devolution of Synchronizers.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny	Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study.	DATE	2010	DBLP BibTeX RDF
1	Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson	Efficiency optimization of integrated DC-DC buck converters.	ICECS	2010	DBLP DOI BibTeX RDF
1	Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny	Performance and Power Aware CMP Thread Allocation Modeling.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser	Threads vs. caches: Modeling the behavior of parallel workloads.	ICCD	2010	DBLP DOI BibTeX RDF
1	Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser	Many-Core vs. Many-Thread Machines: Stay Away From the Valley.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
1	Avinoam Kolodny, Li-Shiuan Peh	Special Section on International Symposium on Networks-on-Chip (NOCS).	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	QNoC asynchronous router.	Integration	2009	DBLP DOI BibTeX RDF
1	Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny	Best of both worlds: A bus enhanced NoC (BENoC).	NOCS	2009	DBLP DOI BibTeX RDF
1	Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter	Packet-level static timing analysis for NoCs.	NOCS	2009	DBLP DOI BibTeX RDF
1	Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny	The design of a latency constrained, power optimized NoC for a 4G SoC.	NOCS	2009	DBLP DOI BibTeX RDF
1	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
1	I. Walter, Israel Cidon, Avinoam Kolodny	BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP.	Computer Architecture Letters	2008	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
1	Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman	Effective Radii of On-Chip Decoupling Capacitors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny	On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	On optimal ordering of signals in parallel wire bundles.	Integration	2008	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
1	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar	Parallel vs. serial on-chip communication.	SLIP	2008	DBLP DOI BibTeX RDF	dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
1	Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Network Delays and Link Capacities in Application-Specific Wormhole NoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Michael Behar, Avi Mendelson, Avinoam Kolodny	Trace cache sampling filter.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	cache utilization, sampling filter, power dissipation, Trace cache
1	Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Access Regulation to Hot-Modules in Wormhole NoCs.	NOCS	2007	DBLP DOI BibTeX RDF	SoC, resource management, Network on-Chip, hotspot, wormhole
1	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
1	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Avinoam Kolodny	Networks on chips: keeping up with Rent's rule and Moore's law.	SLIP	2007	DBLP DOI BibTeX RDF	routing, timing, interconnect, power, on-chip network, wires
1	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Routing table minimization for irregular mesh NoCs.	DATE	2007	DBLP DOI BibTeX RDF
1	Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu	Maximum effective distance of on-chip decoupling capacitors in power distribution grids.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power distribution grids, decoupling capacitors, power distribution systems
1	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Efficient link capacity and QoS design for network-on-chip.	DATE	2006	DBLP DOI BibTeX RDF
1	Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman	On-die decoupling capacitance: frequency domain analysis of activity radius.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Noam Dolev, Avner Kornfeld, Avinoam Kolodny	Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology.	Journal of Circuits, Systems, and Computers	2005	DBLP DOI BibTeX RDF
1	Michael Behar, Avi Mendelson, Avinoam Kolodny	Trace Cache Sampling Filter.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny	On-chip power distribution grids with multiple supply voltages for high performance integrated circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple power supply voltages, power distribution grids, decoupling capacitors, power distribution systems
1	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	QNoC: QoS architecture and design process for network on chip.	Journal of Systems Architecture	2004	DBLP DOI BibTeX RDF
1	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Cost considerations in network on chip.	Integration	2004	DBLP DOI BibTeX RDF
1	Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir	Interconnect-power dissipation in a microprocessor.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect power, wire spacing, routing, low-power design
1	Y. Elboim, Avinoam Kolodny, Ran Ginosar	A clock-tuning circuit for system-on-chip.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	O. Milter, Avinoam Kolodny	Crosstalk noise reduction in synthesized digital logic circuits.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.	VLSI-SOC	2003	DBLP BibTeX RDF

Publications of "Avinoam Kolodny" ( http://dblp.L3S.de/Authors/Avinoam_Kolodny )